ZHCSDL7B November   2014  – March 2016 AMC7834

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics—DAC Specifications
    6. 6.6  Electrical Characteristics—ADC, Current and Temperature Sensor Specifications
    7. 6.7  Electrical Characteristics—General Specifications
    8. 6.8  Serial Interface Timing Requirements
    9. 6.9  Switching Characteristics—DAC Specifications
    10. 6.10 Switching Characteristics—ADC, Current and Temperature Sensor Specifications
    11. 6.11 Switching Characteristics—General Specifications
    12. 6.12 Typical Characteristics
      1. 6.12.1 Typical Characteristics: DAC
      2. 6.12.2 Typical Characteristics: ADC
      3. 6.12.3 Typical Characteristics: Current Sense
      4. 6.12.4 Typical Characteristics: Temperature Sensor
      5. 6.12.5 Typical Characteristics: Reference
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converters (DACs)
        1. 7.3.1.1 DAC Configuration
          1. 7.3.1.1.1 Bipolar DACs (DAC1, DAC2, DAC3, and DAC4)
          2. 7.3.1.1.2 Auxiliary DACs (AUXDAC1, AUXDAC2, AUXDAC3, and AUXDAC4)
        2. 7.3.1.2 DAC Register Structure
        3. 7.3.1.3 DAC Clamp Operation
      2. 7.3.2 Analog-to-Digital Converter (ADC)
        1. 7.3.2.1 External Analog Inputs
        2. 7.3.2.2 Internal Bipolar DAC Monitoring Inputs
        3. 7.3.2.3 ADC Sequencing
      3. 7.3.3 Temperature Sensors
        1. 7.3.3.1 Internal Temperature Sensor
        2. 7.3.3.2 Remote Temperature Sensors
      4. 7.3.4 Current Sensors
      5. 7.3.5 Drain Switch Control
      6. 7.3.6 Programmable Out-of-Range Alarms
        1. 7.3.6.1 ADC Internal Monitoring Input Out-of-Range Alarm
        2. 7.3.6.2 Current-Sense Out-of-Range Alarm
        3. 7.3.6.3 Temperature Sensors Out-of-Range Alarm
        4. 7.3.6.4 Bipolar DACs High Alarm
        5. 7.3.6.5 AVSS Detection Alarm
        6. 7.3.6.6 AVDD Detection Alarm
        7. 7.3.6.7 Hysteresis
        8. 7.3.6.8 False-Alarm Protection
      7. 7.3.7 Reference Specifications
        1. 7.3.7.1 Internal Reference Operation
        2. 7.3.7.2 External Reference Operation
      8. 7.3.8 General Purpose I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Open-Loop Mode
      2. 7.4.2 Closed-Loop Mode
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1  Power Mode: Address 0x02
        1. 7.6.1.1 Power Mode Register (address = 0x02) [reset = 0x000]
      2. 7.6.2  Device Identification: Address 0x04 through 0x0C
        1. 7.6.2.1 Device ID Register (address = 0x04) [reset = 0x0C34]
        2. 7.6.2.2 Version ID Register (address = 0x06) [reset = 0x0001]
        3. 7.6.2.3 Vendor ID Register (address = 0x0C) [reset = 0x0451]
      3. 7.6.3  General Device Configuration: Address 0x10 through 0x16
        1. 7.6.3.1 AMC Configuration 0 Register (address = 0x10) [reset = 0x0300]
        2. 7.6.3.2 AMC Configuration 1 Register (address = 0x11) [reset = 0x036A]
        3. 7.6.3.3 ADC MUX Register (address = 0x12) [reset = 0x0000]
        4. 7.6.3.4 Closed Loop Settling Time Register (address = 0x14) [reset = 0x2222]
        5. 7.6.3.5 DAC Sync Register (address = 0x15) [reset = 0x0000]
        6. 7.6.3.6 DAC Range Register (address = 0x16) [reset = 0x0000]
      4. 7.6.4  Clamp and Alarm Configuration: Address 0x17 through 0x1B
        1. 7.6.4.1 CLAMP Configuration Register (address = 0x17) [reset = 0x003F]
        2. 7.6.4.2 SLEEP1 Configuration Register (address = 0x18) [reset = 0xFF00]
        3. 7.6.4.3 SLEEP2 Configuration Register (address = 0x19) [reset = 0xFF00]
        4. 7.6.4.4 ALARMOUT Clamp Register (address = 0x1A) [reset = 0x0000]
        5. 7.6.4.5 ALARMOUT Configuration Register (address = 0x1B) [reset = 0x0000]
      5. 7.6.5  Conversion Trigger: Address 0x1C
        1. 7.6.5.1 DAC and ADC Trigger Register (address = 0x1C) [reset = 0x0000]
      6. 7.6.6  Reset: Address 0x1D
        1. 7.6.6.1 Software Reset Register (address = 0x1D) [reset = 0x0000]
      7. 7.6.7  Device Status: Address 0x1E and 0x1F
        1. 7.6.7.1 Alarm Status Register (address = 0x1E) [reset = 0x0000]
        2. 7.6.7.2 General Status Register (address = 0x1F) [reset = 0x0000]
      8. 7.6.8  ADC Data: Address 0x20 through 0x2F
        1. 7.6.8.1 ADCn-Internal-Data Register (address = 0x20 to 0x23) [reset = 0x0000]
        2. 7.6.8.2 ADCn-External-Data Register (address = 0x24 to 0x27) [reset = 0x0000]
        3. 7.6.8.3 CSn-Data Register (address = 0x28 to 0x2B) [reset = 0x0000]
        4. 7.6.8.4 LT-Data Register (address = 0x2D) [reset = 0x0000]
        5. 7.6.8.5 RTn-Data Register (address = 0x2E to 0x2F) [reset = 0x0000]
      9. 7.6.9  DAC Data: Address 0x30 through 0x37
        1. 7.6.9.1 DACn-Data Register (address = 0x30 to 0x33) [reset = 0x0000]
        2. 7.6.9.2 AUXDACn-Data Register (address = 0x34 to 0x37) [reset = 0x0000]
      10. 7.6.10 Closed-Loop Control: Address 0x38 through 0x3B
        1. 7.6.10.1 ClosedLoopn Register (address = 0x38 to 0x3B) [reset = 0x0000]
      11. 7.6.11 Alarm Threshold Configuration: Address 0x40 through 0x4F
        1. 7.6.11.1 ADCINTn/CSn-Upper-Threshold Register (address = 0x40, 0x42, 0x44 and 0x46) [reset = 0x0FFF]
        2. 7.6.11.2 ADCINTn/CSn-Lower-Threshold Register (address = 0x41, 0x43, 0x45 and 0x47) [reset = 0x0000]
        3. 7.6.11.3 TS-Upper-Threshold Register (address = 0x48, 0x4A and 0x4C) [reset = 0x07FF]
        4. 7.6.11.4 TS-Lower-Threshold Register (address = 0x49, 0x4B and 0x4D) [reset = 0x0800]
        5. 7.6.11.5 DACnn-Upper-Threshold Register (address = 0x4E and 0x4F) [reset = 0x0FFF]
      12. 7.6.12 Alarm Hysteresis Configuration: Address 0x50 and 0x56
        1. 7.6.12.1 ADCINTn/CSn-Hysteresis Register (address = 0x50 to 0x53) [reset = 0x0008]
        2. 7.6.12.2 LT-Hysteresis Register (address = 0x54) [reset = 0x0008]
        3. 7.6.12.3 RTn-Hysteresis Register (address = 0x55 to 0x56) [reset = 0x0008]
      13. 7.6.13 GPIO: Address 0x58
        1. 7.6.13.1 GPIO Register (address = 0x58) [reset = 0x000F]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ADC Input Conditioning
        2. 8.2.2.2 DAC Output Range Selection
        3. 8.2.2.3 Temperature Sensing Applications
        4. 8.2.2.4 Current Sensing Applications
      3. 8.2.3 Application Performance Curve
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initialization Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

5 Pin Configuration and Functions

RTQ Package
56-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
ADC1 48 I Analog inputs channels. These channels are used for general monitoring. The input range of these pins is 0 to Vref.
ADC2 47 I
ADC3 46 I
ADC4 45 I
AGND1 17 — Analog ground. These pins are the ground reference point for all analog circuitry on the device. Connect the AGND1, AGND2, AGND3, and AGND4 pins to the same potential (AGND). Ideally, the analog and digital grounds should be at the same potential (GND) and must not differ by more than ±0.3 V.
AGND2 22 —
AGND3 35 —
AGND4 43 —
ALARMOUT 2 O ALARMOUT is an open drain global alarm output. An external 10 kΩ pullup resistor to a voltage no higher than AVDD is required. The ALARMOUT output polarity is defined through the ALARMOUT-POLARITY bit in register 0x1B. The default polarity is active low.
AUXDAC1 15 O Auxiliary DAC Outputs. The power-on-reset and clamp voltage for these DACs is always AGND.
AUXDAC2 16 O
AUXDAC3 18 O
AUXDAC4 19 O
AVCC 14 — Positive analog power supply for the auxiliary DACs.
AVDD1 26 — Analog supply voltage (4.5 V to 5.5 V). Connect the AVDD1 and AVDD2 pins to the same potential (AVDD). These pins must have the same value as the DVDD pin.
AVDD2 44 —
AVSS 25 — Lowest potential in the system. This pin is typically tied to a negative supply voltage. If all the bipolar DACs are set to operate in positive output ranges can be connected to the analog ground.
CS 8 I Active low serial data enable. This input is the frame synchronization signal for the serial data. When this signal goes low, it enables the serial interface input shift register.
D1+ 52 I Remote temperature sensor D1. This pin is a positive input when D1 is enabled. This pin can be left unconnected if unused.
D1– 51 I Remote temperature sensor D1. This pin is a negative input when D1 is enabled. This pin can be left unconnected if unused. Pins D1– and D2– are internally shorted.
D2+ 50 I Remote temperature sensor D2. This pin is a positive input when D2 is enabled. This pin can be left unconnected if unused.
D2– 49 I Remote temperature sensor D2. This pin is a negative input when D2 is enabled. This pin can be left unconnected if unused. Pins D1– and D2– are internally shorted.
DAC1 23 O Bipolar DAC outputs 1 and 2. These DACs share the same range and clamp voltage.
DAC2 24 O
DAC3 27 O Bipolar DAC outputs 3 and 4. These DACs share the same range and clamp voltage.
DAC4 28 O
DACTRIG 6 I DAC trigger active low control input. When the DACTRIG pin is low, the contents of the DAC data registers are transferred to the DAC active registers. The DAC outputs update only after the DAC active registers have been loaded. This pin is only operational in open loop current sensing mode.
DAV/ADC_RDY 1 O The DAV/ADC_RDY pin is in high-impedance mode by default and must be enabled through the DAVPIN-EN bit in register 0x11 to access the DAV or ADC_RDY functionality.
DAV is an active low ADC synchronization signal. A 20 µs pulse (active low) on this pin is used to indicate the end of a conversion sequence. Alternatively the pin can be set to operate as ADC_RDY through the DAVPIN-SEL bit in register 0x11. ADC_RDY is an active high synchronization signal used to indicate when the ADC is in the READY state.
DGND 11 — Digital ground. This pin is the ground reference point for all digital circuitry on the device. Ideally, the analog and digital grounds should be at the same potential (GND) and must not differ by more than ±0.3 V.
DVDD 13 — Digital supply voltage (4.5 V to 5.5 V). This pin must be the same value as the AVDD pins.
GPIO1 56 I/O General-purpose digital I/Os. These pins are bidirectional open-drain, digital I/Os and requires an external 10 kΩ pullup resistor to a voltage no higher than AVDD. If unused, the GPIO pins should be connected to ground.
GPIO2 55 I/O
GPIO3 54 I/O
GPIO4 53 I/O
IOVDD 12 — IO supply voltage (1.7 V to 3.6 V). This pin sets the I/O operating voltage and threshold levels.
PAVDD 41 — Power supply for the PA_ON control signal (4 V to 20 V).
PA_ON 40 O PA_ON is a synchronization signal capable of driving an external PMOS switch and controlling the flow of drain current to a power amplifier (PA) transistor. The PA_ON pin has an internal 120 kΩ pull-up resistor to the PAVDD pin. The maximum output voltage is set by the PAVDD pin and limited to 20 V. For drain voltages higher than 20 V, tying the PAVDD pin to the AVDD pins and scaling the control signal externally is recommended. The PA_ON signal state can be set through a register write but it can also be configured to trigger automatically in the case of an ALARM event or when any of the SLEEP signals is activated.
REF_CMP 42 I/O Reference compensation capacitor connection. Connect a 4.7 μF capacitor between this pin and the AGND4 pin for ADC reference compensation.
REF_IN 20 I Reference input to the device. This pin can be connected to the REF_OUT pin to use the device internal reference or alternatively to an external voltage reference source.
REF_OUT 21 O Internal voltage reference output. Connect this pin directly to the REF_IN pin to operate the device in internal reference mode. An external buffer amplifier with a high impedance input is required to drive an external load. This pin can be left unconnected.
RESET 5 I Active low reset input. Logic low on this pin causes the device to perform a hardware reset.
SCLK 7 I Serial interface clock.
SDI 9 I Serial interface data input. Data is clocked into the input shift register on each rising edge of the SCLK pin.
SDO 10 O Serial interface data output. The SDO pin is in high impedance when the CS pin is high. Data is clocked out of the input shift register on each falling edge of the SCLK pin.
SENSE1+ 39 I Current sense 1 external sense resistor power connection
SENSE1– 38 I Current sense 1 external sense resistor load connection
SENSE2+ 37 I Current sense 2 external sense resistor power connection
SENSE2– 36 I Current sense 2 external sense resistor load connection
SENSE3+ 34 I Current sense 3 external sense resistor power connection
SENSE3– 33 I Current sense 3 external sense resistor load connection
SENSE4+ 32 I Current sense 4 external sense resistor power connection
SENSE4– 31 I Current sense 4 external sense resistor load connection
SLEEP1 3 I Active high asynchronous power down digital input 1. The power down functions of this pin are register configurable.
SLEEP2 4 I Active high asynchronous power down digital input 2. The power down functions of this pin are register configurable.
VCLAMP1 30 I Power-on reset and clamp voltage control input for bipolar DACs 1 and 2. The resulting power-on reset (POR) and clamp voltage value is given by Equation 1.
Equation 1. CLAMP = –3 × VCLAMP[1:2]
VCLAMP2 29 I Power-on reset and clamp voltage control input for bipolar DACs 3 and 4. The resulting POR and clamp voltage value is given by Equation 1.
Thermal Pad — The thermal pad is located on the bottom-side of the device package. The thermal pad should be tied to the same potential as the AVSS pin for optimal thermal dissipation. Alternatively, the thermal pad can be left unconnected.
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