ZHCSDQ0C March   2015  – August 2018 LP8758-B0

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化原理图
    1.     效率与输出电流 (VIN = 3.7V)
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameter
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Buck Information
        1. 8.1.1.1 Operating Modes
        2. 8.1.1.2 Features
        3. 8.1.1.3 Programmability
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multi-Phase DC-DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Multi-Phase Operation and Phase Adding/Shedding
        3. 8.3.1.3 Transition Between PWM and PFM Modes
        4. 8.3.1.4 Multi-Phase Switcher Configurations
        5. 8.3.1.5 Buck Converter Load Current Measurement
        6. 8.3.1.6 Spread-Spectrum Mode
      2. 8.3.2 Power-Up
      3. 8.3.3 Regulator Control
        1. 8.3.3.1 Enabling and Disabling Regulator
        2. 8.3.3.2 Changing Output Voltage
      4. 8.3.4 Device Reset Scenarios
      5. 8.3.5 Diagnosis and Protection Features
        1. 8.3.5.1 Warnings for Diagnosis (Interrupt)
          1. 8.3.5.1.1 Output Current Limit
          2. 8.3.5.1.2 Thermal Warning
        2. 8.3.5.2 Protection (Regulator Disable)
          1. 8.3.5.2.1 Short-Circuit and Overload Protection
          2. 8.3.5.2.2 Thermal Shutdown
        3. 8.3.5.3 Fault (Power Down)
          1. 8.3.5.3.1 Undervoltage Lockout
      6. 8.3.6 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  DEV_REV
        2. 8.6.1.2  OTP_REV
        3. 8.6.1.3  BUCK0_CTRL1
        4. 8.6.1.4  BUCK0_CTRL2
        5. 8.6.1.5  BUCK1_CTRL2
        6. 8.6.1.6  BUCK2_CTRL2
        7. 8.6.1.7  BUCK3_CTRL2
        8. 8.6.1.8  BUCK0_VOUT
        9. 8.6.1.9  BUCK0_FLOOR_VOUT
        10. 8.6.1.10 BUCK0_DELAY
        11. 8.6.1.11 RESET
        12. 8.6.1.12 CONFIG
        13. 8.6.1.13 INT_TOP
        14. 8.6.1.14 INT_BUCK_0_1
        15. 8.6.1.15 INT_BUCK_2_3
        16. 8.6.1.16 TOP_STAT
        17. 8.6.1.17 BUCK_0_1_STAT
        18. 8.6.1.18 BUCK_2_3_STAT
        19. 8.6.1.19 TOP_MASK
        20. 8.6.1.20 BUCK_0_1_MASK
        21. 8.6.1.21 BUCK_2_3_MASK
        22. 8.6.1.22 SEL_I_LOAD
        23. 8.6.1.23 I_LOAD_2
        24. 8.6.1.24 I_LOAD_1
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Input Capacitor Selection
          3. 9.2.2.1.3 Output Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息

7.6 I2C Serial Bus Timing Parameter

See(1) and Figure 1.
MIN MAX UNIT
ƒSCL Serial clock frequency Standard mode 100 kHz
Fast mode 400 kHz
Fast mode + 1 MHz
High-speed mode, Cb = 100 pF 3.4 MHz
High-speed mode, Cb = 400 pF 1.7 MHz
tLOW SCL low time Standard mode 4.7 µs
Fast mode 1.3
Fast mode + 0.5
High-speed mode, Cb = 100 pF 160 ns
High-speed mode, Cb = 400 pF 320
tHIGH SCL high time Standard mode 4 µs
Fast mode 0.6
Fast mode + 0.26
High-speed mode, Cb = 100 pF 60 ns
High-speed mode, Cb = 400 pF 120
tSU;DAT Data setup time Standard mode 250 ns
Fast mode 100
Fast mode + 50
High-speed mode 10
tHD;DAT Data hold time Standard mode 0 3.45 µs
Fast mode 0 0.9
Fast mode + 0
High-speed mode, Cb = 100 pF 0 70 ns
High-speed mode, Cb = 400 pF 0 150
tSU;STA Setup time for a start or a repeated start condition Standard mode 4.7 µs
Fast mode 0.6
Fast mode + 0.26
High-speed mode 160 ns
tHD;STA Hold time for a start or a repeated start condition Standard mode 4 µs
Fast mode 0.6
Fast mode + 0.26
High-speed mode 160 ns
tBUF Bus free time between a stop and start condition Standard mode 4.7 µs
Fast mode 1.3
Fast mode + 0.5
tSU;STO Setup time for a stop condition Standard mode 4 µs
Fast mode 0.6
Fast mode + 0.26
High-speed mode 160 ns
trDA Rise time of SDA signal Standard mode 1000 ns
Fast mode 300
Fast mode + 120
High-speed mode, Cb = 100 pF 80
High-speed mode, Cb = 400 pF 160
tfDA Fall time of SDA signal Standard mode 250 ns
Fast mode 250
Fast mode + 120
High-speed mode, Cb = 100 pF 80
High-speed mode, Cb = 400 pF 160
trCL Rise time of SCL signal Standard mode 1000 ns
Fast mode 300
Fast mode + 120
High-speed Mode, Cb = 100 pF 40
High-speed Mode, Cb = 400 pF 80
trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit Standard mode 1000 ns
Fast mode 300
Fast mode + 120
High-speed mode, Cb = 100 pF 80
High-speed mode, Cb = 400 pF 160
tfCL Fall time of a SCL signal Standard mode 300 ns
Fast mode 300
Fast mode + 120
High-speed mode, Cb = 100 pF 40
High-speed mode, Cb = 400 pF 80
Cb Capacitive load for each bus line (SCL and SDA) 400 pF
tSP Pulse width of spike suppressed in SCL and SDA lines (spikes that are less than the indicated width are suppressed) Fast mode, fast mode + 50 ns
High-speed mode 10
(1) Cb refers to the capacitance of one bus line. Cb is expressed in pF units.
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