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ZHCSDS3C May 2015 – April 2018 ADS52J90

PRODUCTION DATA.

7.7 Timing Requirements: Signal Chain

Typical values are at 25°C. AVDD_1P8 = DVDD_1P8 = 1.8 V, DVDD_1P2 = 1.2 V, and external differential load resistance between the LVDS output pair (R_LOAD= 100 Ω), unless otherwise noted. A capacitive load of 4 pF is on the LVDS outputs.

			MIN	TYP	MAX	UNIT
GENERAL
t_AP	Aperture delay			1.6		ns
δt_AP	Aperture delay variation from device to device (at same temperature and supply)			±0.5		ns
t_APJ	Aperture jitter with LVPECL clock as input clock			0.5		ps
ADC TIMING
N_LAT	ADC latency	Default after reset		8.5		Conversion clocks
N_LAT	ADC latency	Low-latency mode		4.5		Conversion clocks
LVDS TIMING
f_F	Frame clock frequency	16-input and 8-input modes		f_C		MHz
f_F	Frame clock frequency	32-input mode		f_C / 2		MHz
D_FRAME	Frame clock duty cycle			50%
N_SER	Number of bits serialization of each ADC word		10		16	Bits
f_D	Output rate of serialized data for 1X output data rate mode, 16-, 8-. and 32-input modes			N_SER × f_C	1000	Mbps
f_D	Output rate of serialized data for 2X output data rate mode, 16-input and 8-input modes			2 × N_SER × f_C	1000	Mbps
f_B	Bit clock frequency			f_D / 2	500	MHz
D_BIT	Bit clock duty cycle			50%
t_D	Data bit duration		1	1000 / f_D		ns
t_PROP	Clock propagation delay⁽⁵⁾			6 × t_D+ 5		ns
δt_PROP	Clock propagation delay variation from device to device (at same temperature and supply)			±2		ns
t_ORF	DOUT, DCLK, FCLK rise and fall time, transition time between –100 mV and +100 mV			0.2		ns
t_OSU	Minimum serial data, serial clock setup time⁽²⁾			t_D / 2 – 0.4		ns
t_OH	Minimum serial data, serial clock hold time⁽²⁾			t_D / 2 – 0.4		ns
t_DV	Minimum data valid window⁽¹⁾⁽²⁾			t_D – 0.65		ns
TX_TRIG TIMING
t_{TX_TRIG_DEL}	Delay between TX_TRIG and TX_TRIGD⁽³⁾		0.5		0.4 × t_S⁽⁴⁾	ns
t_{SU_TX_TRIGD}	Setup time related to latching TX_TRIG relative to the rising edge of the system clock			0.6		ns
t_{H_TX_TRIGD}	Hold time related to latching TX_TRIG relative to the rising edge of the system clock			0.4		ns

(1) The specification for the minimum data valid window is larger than the sum of the minimum setup and hold times because there can be a skew between the ideal transitions of the serial output data with respect to the transition of the bit clock. This skew can vary across channels and across devices. A mechanism to correct this skew can therefore improve the setup and hold timing margins. For example, the LVDS_DCLK_DELAY_PROG control can be used to shift the relative timing of the bit clock with respect to the data.

(2) See Figure 1.

(3) TX_TRIGD is the internally delayed version of TX_TRIG that gets latched on the rising edge of the system clock.

(4) t_S is the system clock period in ns.

(5) See Figure 64 to Figure 68 for the definition of t_PROP in various operating modes.