8.3.10 Interfacing SYNC~ and SYSREF Between the FPGA and ADCs

The SYNC~ and SYSREF signals must be connected to the FPGA and the multiple ADCs in the system. When driving SYNC~ and SYSREF using differential signals, additional interface circuits may be required to decouple the common-mode levels between the FPGA and the ADC. Figure 80 shows an overview of such a scheme for driving the SYNC~ signal from the FPGA to multiple ADCs.

Figure 80. Connection of SYNC~ From the FPGA to the ADCs

The ADC has internal 5-kΩ resistors from the SYNCP and SYNCM pins to an internal reference voltage of 0.7 V. When driven by a differential driver, an interface circuit may be required to match the common-mode voltages between the driver and the ADC. An example circuit is shown in Figure 81 to level-shift from a 1.2-V common-mode voltage at the driver output to the 0.7 V at the ADC input. The 100 Ω at the driver output depicts the differential termination and could be realized inside the FPGA.

Figure 81. Circuit to Level-Shift the Common-Mode Voltage From 1.2 V at the Driver Output to 0.7 V at the ADC Input

For a different driver output common-mode than the one shown in Figure 81, the interface circuit must be modified.

A similar circuit as shown in Figure 81 can also be used to interface the SYSREF signals to the ADC. As shown in Figure 82, the SYSREF signal can also be driven using an ac-coupling scheme. The external components are chosen for a case where the SYSREF source drives only one ADC. The values of these components must be changed if the signal is interfaced to multiple ADCs (contact the factory for details).

Figure 82. AC-Coupling Scheme for SYSREF (do not use for SYNC~)

Figure 83. Transient of SYSREF With AC-Coupling

The 50-kΩ and 30-kΩ external resistors along with the two 5-kΩ resistors internal to the ADC form a voltage divider circuit to generate a negative differential offset at the ADC SYSREF input when SYSREF is low. A high-going pulse on the SYSREF_SRC signal passes through the ac-coupling capacitor. The ac-coupling capacitor and the resistors form a high-pass filter and cause the SYSREF_ADC signal to droop towards their quiescent values over time (denoted by the dotted lines in Figure 83). However, if the high width of SYSREF is much lower than the time constant of the filter, the circuit is able to pass the pulse properly.

The SYNC~ and SYSREF signals also can be driven using single-ended LVCMOS levels, which can be done by driving the P side with the LVCMOS level and connecting the M side to ground as shown in Figure 84. When driven in this manner, the internal 5-kΩ resistor (connecting the P and M pins to the 0.7-V node) is disconnected from the pins.

Figure 84. Single-Ended Driving Circuit for SYNC~ and SYSREF