ZHCSDS3C May   2015  – April 2018 ADS52J90

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Digital Characteristics
    7. 7.7  Timing Requirements: Signal Chain
    8. 7.8  Timing Requirements: JESD Interface
    9. 7.9  Timing Requirements: Serial Interface
    10. 7.10 Typical Characteristics
    11. 7.11 Typical Characteristics: JESD Interface
    12. 7.12 Typical Characteristics: Contour Plots
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Connection of the External Inputs to the Input Pins
      2. 8.3.2  Input Multiplexer and Sampler
      3. 8.3.3  Analog-to-Digital Converter (ADC)
      4. 8.3.4  Device Synchronization Using TX_TRIG
      5. 8.3.5  Digital Processing
        1. 8.3.5.1 Digital Offset
          1. 8.3.5.1.1 Manual Offset Correction
          2. 8.3.5.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)
          3. 8.3.5.1.3 Digital Averaging
          4. 8.3.5.1.4 Digital Gain
          5. 8.3.5.1.5 Digital HPF
      6. 8.3.6  Data Formatting
      7. 8.3.7  Serializer and LVDS Interface
      8. 8.3.8  LVDS Buffers
      9. 8.3.9  JESD204B Interface
        1. 8.3.9.1 Overview
        2. 8.3.9.2 Link Configuration
        3. 8.3.9.3 JESD Version and Subclass
        4. 8.3.9.4 Transport Layer
          1. 8.3.9.4.1 User Data Format
          2. 8.3.9.4.2 Transport Layer Test Patterns
        5. 8.3.9.5 Scrambler
        6. 8.3.9.6 Data Link Layer
          1. 8.3.9.6.1 Code Group Synchronization (CGS)
          2. 8.3.9.6.2 Initial Lane Alignment (ILA)
          3. 8.3.9.6.3 Lane and Frame Alignment Monitoring
          4. 8.3.9.6.4 Link Layer Test Modes
        7. 8.3.9.7 Deterministic Latency
          1. 8.3.9.7.1 Synchronization Using SYNC~ and SYSREF
          2. 8.3.9.7.2 Latency
          3. 8.3.9.7.3 Multiframe Size
        8. 8.3.9.8 JESD Physical Layer
          1. 8.3.9.8.1 CML Buffer
          2. 8.3.9.8.2 Jitter Considerations
      10. 8.3.10 Interfacing SYNC~ and SYSREF Between the FPGA and ADCs
      11. 8.3.11 Clock Input
      12. 8.3.12 Analog Input and Driving Circuit
        1. 8.3.12.1 Signal Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Modes
      2. 8.4.2 ADC Resolution Modes
      3. 8.4.3 LVDS and JESD Interface Modes
      4. 8.4.4 LVDS Serialization and Output Data Rate Modes
      5. 8.4.5 Power Modes
      6. 8.4.6 LVDS Test Pattern Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Operation
        1. 8.5.1.1 Serial Register Write Description
        2. 8.5.1.2 Register Readout
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing with the 16-Input Mode
        2. 9.2.2.2 Designing with the 32-Input Mode
        3. 9.2.2.3 Designing with the 8-Input Mode
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Power Supply, Grounding, and Bypassing
    2. 11.2 Layout Guidelines
    3. 11.3 Layout Example
  12. 12Register Map
    1. 12.1 ADC Registers
      1. 12.1.1 Description of Registers
        1. 12.1.1.1  Register 0h (address = 0h)
          1. Table 47. Register 0h Field Descriptions
        2. 12.1.1.2  Register 1h (address = 1h)
          1. Table 48. Register 1h Field Descriptions
        3. 12.1.1.3  Register 2h (address = 2h)
          1. Table 51. Register 2h Field Descriptions
        4. 12.1.1.4  Register 3h (address = 3h)
          1. Table 53. Register 3h Field Descriptions
        5. 12.1.1.5  Register 4h (address = 4h)
          1. Table 54. Register 4h Field Descriptions
        6. 12.1.1.6  Register 5h (address = 5h)
          1. Table 55. Register 5h Field Descriptions
        7. 12.1.1.7  Register 7h (address = 7h)
          1. Table 56. Register 7h Field Descriptions
        8. 12.1.1.8  Register 8h (address = 8h)
          1. Table 57. Register 8h Field Descriptions
        9. 12.1.1.9  Register Ah (address = Ah)
          1. Table 58. Register Ah Field Descriptions
        10. 12.1.1.10 Register Bh (address = Bh)
          1. Table 59. Register Bh Field Descriptions
        11. 12.1.1.11 Register Dh (address = Dh)
          1. Table 60. Register Dh Field Descriptions
        12. 12.1.1.12 Register Eh (address = Eh)
          1. Table 61. Register Eh Field Descriptions
        13. 12.1.1.13 Register Fh (address = Fh)
          1. Table 62. Register Fh Field Descriptions
        14. 12.1.1.14 Register 10h (address = 10h)
          1. Table 63. Register 10h Field Descriptions
        15. 12.1.1.15 Register 11h (address = 11h)
          1. Table 64. Register 11h Field Descriptions
        16. 12.1.1.16 Register 12h (address = 12h)
          1. Table 65. Register 12h Field Descriptions
        17. 12.1.1.17 Register 13h (address = 13h)
          1. Table 66. Register 13h Field Descriptions
        18. 12.1.1.18 Register 14h (address = 14h)
          1. Table 67. Register 14h Field Descriptions
        19. 12.1.1.19 Register 15h (address = 15h)
          1. Table 68. Register 15h Field Descriptions
        20. 12.1.1.20 Register 17h (address = 17h)
          1. Table 69. Register 17h Field Descriptions
        21. 12.1.1.21 Register 18h (address = 18h)
          1. Table 70. Register 18h Field Descriptions
        22. 12.1.1.22 Register 19h (address = 19h)
          1. Table 71. Register 19h Field Descriptions
        23. 12.1.1.23 Register 1Ah (address = 1Ah)
          1. Table 72. Register 1Ah Field Descriptions
        24. 12.1.1.24 Register 1Bh (address = 1Bh)
          1. Table 73. Register 1Bh Field Descriptions
        25. 12.1.1.25 Register 1Ch (address = 1Ch)
          1. Table 74. Register 1Ch Field Descriptions
        26. 12.1.1.26 Register 1Dh (address = 1Dh)
          1. Table 75. Register 1Dh Field Descriptions
        27. 12.1.1.27 Register 1Eh (address = 1Eh)
          1. Table 76. Register 1Eh Field Descriptions
        28. 12.1.1.28 Register 1Fh (address = 1Fh)
          1. Table 77. Register 1Fh Field Descriptions
        29. 12.1.1.29 Register 20h (address = 20h)
          1. Table 78. Register 20h Field Descriptions
        30. 12.1.1.30 Register 21h (offset = 21h)
          1. Table 79. Register 21h Field Descriptions
        31. 12.1.1.31 Register 23h (register = 23h)
          1. Table 80. Register 23h Field Descriptions
        32. 12.1.1.32 Register 24h (address = 24h)
          1. Table 81. Register 24h Field Descriptions
        33. 12.1.1.33 Register 25h (address = 25h)
          1. Table 82. Register 25h Field Descriptions
        34. 12.1.1.34 Register 26h (address = 26h)
          1. Table 83. Register 26h Field Descriptions
        35. 12.1.1.35 Register 27h (address = 27h)
          1. Table 84. Register 27h Field Descriptions
        36. 12.1.1.36 Register 28h (address = 28h)
          1. Table 85. Register 28h Field Descriptions
        37. 12.1.1.37 Register 29h (address = 29h)
          1. Table 86. Register 29h Field Descriptions
        38. 12.1.1.38 Register 2Ah (address = 2Ah)
          1. Table 87. Register 2Ah Field Descriptions
        39. 12.1.1.39 Register 2Bh (address = 2Bh)
          1. Table 88. Register 2Bh Field Descriptions
        40. 12.1.1.40 Register 2Ch (address = 2Ch)
          1. Table 89. Register 2Ch Field Descriptions
        41. 12.1.1.41 Register 2Dh (address = 2Dh)
          1. Table 90. Register 2Dh Field Descriptions
        42. 12.1.1.42 Register 2Fh (address = 2Fh)
          1. Table 91. Register 2Fh Field Descriptions
        43. 12.1.1.43 Register 30h (address = 30h)
          1. Table 92. Register 30h Field Descriptions
        44. 12.1.1.44 Register 31h (address = 31h)
          1. Table 93. Register 31h Field Descriptions
        45. 12.1.1.45 Register 32h (address = 32h)
          1. Table 94. Register 32h Field Descriptions
        46. 12.1.1.46 Register 33h (address = 33h)
          1. Table 95. Register 33h Field Descriptions
        47. 12.1.1.47 Register 34h (address = 34h)
          1. Table 96. Register 34h Field Descriptions
        48. 12.1.1.48 Register 35h (address = 35h)
          1. Table 97. Register 35h Field Descriptions
        49. 12.1.1.49 Register 36h (address = 36h)
          1. Table 98. Register 36h Field Descriptions
        50. 12.1.1.50 Register 37h (address = 37h)
          1. Table 99. Register 37h Field Descriptions
        51. 12.1.1.51 Register 38h (address = 38h)
          1. Table 100. Register 38h Field Descriptions
        52. 12.1.1.52 Register 39h (address = 39h)
          1. Table 101. Register 39h Field Descriptions
        53. 12.1.1.53 Register 3Bh (address = 3Bh)
          1. Table 102. Register 3Bh Field Descriptions
        54. 12.1.1.54 Register 3Ch (address = 3Ch)
          1. Table 103. Register 3Ch Field Descriptions
        55. 12.1.1.55 Register 43h (address = 43h)
          1. Table 104. Register 43h Field Descriptions
    2. 12.2 JESD Serial Interface Registers
      1. 12.2.1 Description of JESD Serial Interface Registers
        1. 12.2.1.1  Register 70 (address = 46h)
          1. Table 106. Register 70 Field Descriptions
        2. 12.2.1.2  Register 73 (address = 49h)
          1. Table 107. Register 73 Field Descriptions
        3. 12.2.1.3  Register 74 (address = 4Ah)
          1. Table 108. Register 74 Field Descriptions
        4. 12.2.1.4  Register 75 (address = 4Bh)
          1. Table 109. Register 75 Field Descriptions
        5. 12.2.1.5  Register 77 (address = 4Dh)
          1. Table 110. Register 77 Field Descriptions
        6. 12.2.1.6  Register 80 (address = 50h)
          1. Table 111. Register 80 Field Descriptions
        7. 12.2.1.7  Register 81 (address = 51h)
          1. Table 112. Register 81 Field Descriptions
        8. 12.2.1.8  Register 82 (address = 52h)
          1. Table 113. Register 82 Field Descriptions
        9. 12.2.1.9  Register 83 (address = 53h)
          1. Table 114. Register 83 Field Descriptions
        10. 12.2.1.10 Register 85 (address = 55h)
          1. Table 115. Register 85 Field Descriptions
        11. 12.2.1.11 Register 115 (address = 73h)
          1. Table 116. Register 115 Field Descriptions
        12. 12.2.1.12 Register 116 (address = 74h)
          1. Table 117. Register 116 Field Descriptions
        13. 12.2.1.13 Register 117 (address = 75h)
          1. Table 118. Register 117 Field Descriptions
        14. 12.2.1.14 Register 118 (address = 76h)
          1. Table 119. Register 118 Field Descriptions
        15. 12.2.1.15 Register 119 (address = 77h)
          1. Table 120. Register 119 Field Descriptions
        16. 12.2.1.16 Register 120 (address = 78h)
          1. Table 121. Register 120 Field Descriptions
        17. 12.2.1.17 Register 134 (address = 86h)
          1. Table 122. Register 134 Field Descriptions
        18. 12.2.1.18 Register 135 (address = 87h)
          1. Table 123. Register 135 Field Descriptions
        19. 12.2.1.19 Register 136 (address = 88h)
          1. Table 124. Register 136 Field Descriptions
        20. 12.2.1.20 Register 137 (address = 89h)
          1. Table 125. Register 137 Field Descriptions
        21. 12.2.1.21 Register 138 (address = 8Ah)
          1. Table 126. Register 138 Field Descriptions
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 术语表
  14. 14机械、封装和可订购信息

6 Pin Configuration and Functions

ZZE Package
NFBGA-198 (15 mm × 9 mm)
Top View
ADS52J90 po_sbas623.gif

Pin Functions(2)

PIN I/O DESCRIPTION
NAME NO.
AVDD_1P8 A4, E6, F6, G5, G6, M5, M6, N6, P6, V4 P 1.8-V analog supply voltage
AVSS B4, C4, D4, H5, H6, J5, J6, K5, K6, L5, L6, R4, R5, T4, T5, U4, U6, V6 G Analog ground
CLKM U5 I Differential clock input pins. A single-ended clock is also supported.
See the Clock Input section for further details.
CLKP V5
CML1_OUTM A10 O JESD output lane 1
CML1_OUTP A9
CML2_OUTM B11 O JESD output lane 2
CML2_OUTP A11
CML3_OUTM D11 O JESD output lane 3
CML3_OUTP C11
CML4_OUTM F11 O JESD output lane 4
CML4_OUTP E11
CML5_OUTM V10 O JESD output lane 5
CML5_OUTP V9
CML6_OUTM U11 O JESD output lane 6
CML6_OUTP V11
CML7_OUTM R11 O JESD output lane 7
CML7_OUTP T11
CML8_OUTM N11 O JESD output lane 8
CML8_OUTP P11
DCLKM K11 O LVDS bit clock output
DCLKP J11
DOUTM1 B10 O LVDS data lane 1
DOUTP1 B9
DOUTM2 C10 O LVDS data lane 2
DOUTP2 C9
DOUTM3 D10 O LVDS data lane 3
DOUTP3 D9
DOUTM4 E10 O LVDS data lane 4
DOUTP4 E9
DOUTM5 F10 O LVDS data lane 5
DOUTP5 F9
DOUTM6 G10 O LVDS data lane 6
DOUTP6 G9
DOUTM7 H10 O LVDS data lane 7
DOUTP7 H9
DOUTM8 G11 O LVDS data lane 8
DOUTP8 H11
DOUTM9 M11 O LVDS data lane 9
DOUTP9 L11
DOUTM10 L10 O LVDS data lane 10
DOUTP10 L9
DOUTM11 M10 O LVDS data lane 11
DOUTP11 M9
DOUTM12 N10 O LVDS data lane 12
DOUTP12 N9
DOUTM13 P10 O LVDS data lane 13
DOUTP13 P9
DOUTM14 R10 O LVDS data lane 14
DOUTP14 R9
DOUTM15 T10 O LVDS data lane 15
DOUTP15 T9
DOUTM16 U10 O LVDS data lane 16
DOUTP16 U9
DVDD_1P2 A7, B8, C8, D8, F7, G7, M7, N7, R8, T6, T8, U8, V7 P 1.2-V digital supply voltage
DVDD_1P8 E8, F8, G8, J10, M8, N8, P8 P 1.8-V digital supply voltage
DVSS A8, D7, E7, H7, H8, J7, J8, K7, K8, K10, L7, L8, R6, V8 G Digital ground
FCLKM K9 O LVDS frame clock output
FCLKP J9
INM1 B3 I Differential analog input 1 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP1 A3
INM2 A1 I Differential analog input 2 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP2 A2
INM3 B1 I Differential analog input 3 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP3 B2
INM4 D3 I Differential analog input 4 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP4 C3
INM5 C1 I Differential analog input 5 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP5 C2
INM6 D1 I Differential analog input 6 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP6 D2
INM7 E1 I Differential analog input 7 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP7 E2
INM8 E3 I Differential analog input 8 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP8 E4
INM9 F1 I Differential analog input 9 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP9 F2
INM10 F3 I Differential analog input 10 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP10 F4
INM11 G1 I Differential analog input 11 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP11 G2
INM12 G3 I Differential analog input 12 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP12 G4
INM13 H1 I Differential analog input 13 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP13 H2
INM14 H3 I Differential analog input 14 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP14 H4
INM15 J1 I Differential analog input 15 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP15 J2
INM16 J3 I Differential analog input 16 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP16 J4
INM17 K1 I Differential analog input 17 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP17 K2
INM18 K3 I Differential analog input 18 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP18 K4
INM19 L1 I Differential analog input 19 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP19 L2
INM20 L3 I Differential analog input 20 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP20 L4
INM21 M1 I Differential analog input 21 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP21 M2
INM22 M3 I Differential analog input 22 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP22 M4
INM23 N1 I Differential analog input 23 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP23 N2
INM24 N3 I Differential analog input 24 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP24 N4
INM25 P1 I Differential analog input 25 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP25 P2
INM26 P3 I Differential analog input 26 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP26 P4
INM27 R1 I Differential analog input 27 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP27 R2
INM28 R3 I Differential analog input 28 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP28 T3
INM29 T1 I Differential analog input 29 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP29 T2
INM30 U1 I Differential analog input 30 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP30 U2
INM31 V1 I Differential analog input 31 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP31 V2
INM32 U3 I Differential analog input 32 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP32 V3
NC D5, E5, N5, P5 — Do not connect; leave floating.
PDN_FAST C6 I Fast power-down control pin (active high) with an internal pulldown resistor of 20 kΩ. For active high, a 1.8-V logic level is recommended.
PDN_GBL C7 I Global power-down control input (active high) with an internal pulldown resistor of 20 kΩ. For active high, a 1.8-V logic level is recommended.
SPI_DIG_EN B6 I Reserved for digital functionality. This pin can be left floating or be connected to the 1.8-V supply. This pin has an internal pullup resistor of 20 kΩ.
RESET A6 I Hardware reset pin (active high) with an internal pulldown resistor of 20 kΩ. For active high, a 1.8-V logic level is recommended.
SCLK B7 I Serial interface clock input with an internal pulldown resistor of 20 kΩ. For active high, a 1.8-V logic level is recommended.
SDIN A5 I Serial interface data input with an internal pulldown resistor of 20 kΩ. For active high, a 1.8-V logic level is recommended.
SDOUT C5 O Serial interface data readout. High impedance when readout is disabled. 1.8-V logic level is recommended.
SEN B5 I Serial interface enable with an internal pullup resistor of 20 kΩ. 1.8-V logic level is recommended.
TX_TRIG D6 I 1.8-V logic; a pulse on TX_TRIG must be applied after power-up to ensure that all internal clock dividers are synchronized(1).Has an internal pull-down resistor of 20 kΩ to ground.
SYNCM_SERDES P7 I Frame synchronization input as per JESD204B standard
SYNCP_SERDES R7
SYSREFM_SERDES T7 I Frame clock and local multiframe clock (LMFC) synchronization input as per JESD204B, subclass 1 standard
SYSREFP_SERDES U7
VCM F5 O Common-mode output pin for biasing analog input signals. Connect a 10-µF capacitor to ground.
(1) See the Device Synchronization Using TX_TRIG section for more details on synchronization using TX_TRIG.
(2) If the JESD interface is not used, then do not connect the CMLx, SYNCx, and SYSREFx pins. If the LVDS interface is not used, then do not connect DOUTx, DCLKx, and FCLKx.
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