ZHCSDS3C May 2015 – April 2018 ADS52J90
PRODUCTION DATA.
The device supports three input modes: a 16-input, a 32-input, and an 8-input mode using the SEL_CH[2:0] register controls. See Table 49 for a listing of register bits that select the 8-, 16-, and 32-input modes. Using the same set of 16 ADCs, the three modes can be used to convert 16, 32, or 8 input channels, respectively. The performance of the ADC itself depends on the conversion clock frequency, which has a different relationship to the system clock and sampling rates in each of the three modes. Although the ADCs are common to all three modes, the manner in which the ADCs are used determines unique performance characteristics in each mode. For example, the 8-input mode can have significant interleaving spurs. Additionally, in the 8-input mode, the conversion phases of two adjacent ADCs are offset by one system clock period. The switching operation in one ADC can affect the performance of the adjacent ADC especially at higher input frequencies. For this reason, only 10-bit ADC resolution is supported in the 8-input mode. The restrictions when operating in the different input modes are listed in Table 30.
ANALOG INPUT MODE | ADC RESOLUTIONS SUPPORTED (Bits) | LVDS DATA RATE MODES SUPPORTED |
---|---|---|
16 | 10, 12, 14 | 1X, 2X |
32 | 10, 12, 14 | 1X |
8 | 10 | 1X, 2X |