9.3 Do's and Don'ts

Driving the inputs (analog or digital) beyond the power-supply rails. For device reliability, an input must not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits, even on a transient basis, can cause faulty or erratic operation and can impair device reliability.

Driving the device signal input with an excessively high level signal. The device offers consistent and fast overload recovery for an overload of upto 6 dBFS. For very large overload signals (> 6 dB of the linear input signal range), TI recommends back-to-back Schottky clamping diodes at the input to limit the amplitude of the input signal.

Using a clock source with excessive jitter, an excessively long input clock signal trace, or having other signals coupled to the ADC clock signal trace. These situations cause the sampling instant vary, causing an excessive output noise and a reduction in SNR performance. For a system with multiple devices, the clock tree scheme must be used to apply an ADC clock. Excessive clock delay mismatch between devices can also lead to latency mismatch and functional failure at the system level.

LVDS routing length mismatch. The routing length of all LVDS lines routing to the FPGA must be matched to avoid any timing-related issues. For systems with multiple devices, the LVDS serialized data clock (DCLKP, DCLKM) and the frame clock (FCLKP, FCLKM) of each individual device must be used to deserialize the corresponding LDVS serialized data (DOUTP, DOUTM).

Failure to provide adequate heat removal. Use the appropriate thermal parameter listed in the Thermal Information table and an ambient, board, or case temperature in order to calculate device junction temperature. A suitable heat removal technique must be used to keep the device junction temperature below the maximum limit of 105°C.