11.2 Layout Guidelines

High-speed, mixed-signal devices are sensitive to various types of noise coupling. One primary source of noise is the switching noise from the serializer and the output buffer and drivers. For the device, care must be taken to ensure that the interaction between the analog and digital supplies within the device is kept to a minimal amount. The extent of noise coupled and transmitted from the digital and analog sections depends on the effective inductances of each of the supply and ground connections. Smaller effective inductances of the supply and ground pins result in better noise suppression. For this reason, multiple pins are used to connect each supply and ground sets. Low inductance properties must be maintained throughout the design of the PCB layout by use of proper planes and layer thickness.

To avoid noise coupling through supply pins, TI recommends keeping sensitive input pins (such as the INM and INP pins) away from the supply planes. For example, do not route the traces or vias connected to these pins across the supply planes. That is, avoid the power planes under the INM and INP pins.

Some layout guidelines associated with the layout of the high speed interfaces are listed below:

• The length of the positive and negative traces of a differential pair must be matched to within 2 mils of each other.
• Each differential pair length must be matched within 10 mils of other differential pairs.
• When the ADC is used on the same printed circuit board (PCB) with a digital intensive component (such as an FPGA or ASIC), separate digital and analog ground planes must be used. Do not overlap these separate ground planes to minimize undesired coupling.
• Connect decoupling capacitors directly to ground and place these capacitors close to the ADC power pins and the power-supply pins to filter high-frequency current transients directly to the ground plane.
• Ground and power planes must be wide enough to keep the impedance very low. In a multilayer PCB, one layer must be dedicated to each ground and power plane.
• All high-speed traces must be routed straight with minimum bends. Where a bend is necessary, avoid making very sharp right-angle bends in the trace.
• In order to maintain proper LVDS timing, all LVDS traces must follow a controlled impedance design. In addition, all LVDS trace lengths must be equal and symmetrical; TI recommends keeping trace length variations less than 150 mil (0.150 inch or 3.81 mm).
• When routing CML lines, the traces must be designed for a controlled impedance of 50 Ω. The routing of different lines must be matched as much as possible to minimize the inter-lane skew. However, trace length matching is less critical for the JESD interface as compared to the LVDS interface.

Additional details on the NFBGA PCB layout techniques can be found in the Texas Instruments application report, MicroStar BGA Packaging Reference Guide (SSYZ015), available from www.ti.com.