ZHCSDS7A May   2015  – June 2015 LDC1101

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Digital Interface
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Sensor Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 Measurement Modes
      2. 8.4.2 RP+L Measurement Mode
        1. 8.4.2.1 RPMIN and RPMAX
        2. 8.4.2.2 Programmable Internal Time Constants
        3. 8.4.2.3 RP+L Mode Measurement Sample Rate
      3. 8.4.3 High Resolution L (LHR) Measurement Mode
      4. 8.4.4 Reference Count Setting
      5. 8.4.5 L-Only Measurement Operation
      6. 8.4.6 Minimum Sensor Frequency and Watchdog Setting
      7. 8.4.7 Low Power Modes
        1. 8.4.7.1 Shutdown Mode
        2. 8.4.7.2 Sleep Mode
      8. 8.4.8 Status Reporting
      9. 8.4.9 Switch Functionality and INTB Reporting
    5. 8.5 Programming
      1. 8.5.1 SPI Programming
    6. 8.6 Register Maps
      1. 8.6.1  Individual Register Listings
      2. 8.6.2  Register RP_SET (address = 0x01) [reset = 0x07]
      3. 8.6.3  Register TC1 (address = 0x02) [reset = 0x90]
      4. 8.6.4  Register TC2 (address = 0x03) [reset = 0xA0]
      5. 8.6.5  Register DIG_CONF (address = 0x04) [reset = 0x03]
      6. 8.6.6  Register ALT_CONFIG (address = 0x05) [reset = 0x00]
      7. 8.6.7  Register RP_THRESH_HI_LSB (address = 0x06) [reset = 0x00]
      8. 8.6.8  Register RP_THRESH_HI_MSB (address = 0x07) [reset = 0x00]
      9. 8.6.9  Register RP_THRESH_LO_LSB (address = 0x08) [reset = 0x00]
      10. 8.6.10 Register RP_THRESH_LO_MSB (address = 0x09) [reset = 0x00]
      11. 8.6.11 Register INTB_MODE (address = 0x0A) [reset = 0x00]
      12. 8.6.12 9.Register START_CONFIG (address = 0x0B) [reset = 0x01]
      13. 8.6.13 Register D_CONFIG (address = 0x0C) [reset = 0x00]
      14. 8.6.14 Register L_THRESH_HI_LSB (address = 0x16) [reset = 0x00]
      15. 8.6.15 Register L_THRESH_HI_MSB (address = 0x17) [reset = 0x00]
      16. 8.6.16 Register L_THRESH_LO_LSB (address = 0x18) [reset = 0x00]
      17. 8.6.17 Register L_THRESH_LO_MSB (address = 0x19) [reset = 0x00]
      18. 8.6.18 Register STATUS (address = 0x020 [reset = 0x00]
      19. 8.6.19 Register RP_DATA_LSB (address = 0x21) [reset = 0x00]
      20. 8.6.20 Register RP_DATA_MSB (address = 0x22) [reset = 0x00]
      21. 8.6.21 Register L_DATA_LSB (address = 0x23) [reset = 0x00]
      22. 8.6.22 Register L_DATA_MSB (address = 0x24) [reset = 0x00]
      23. 8.6.23 Register LHR_RCOUNT_LSB (address = 0x30) [reset = 0x00]
      24. 8.6.24 Register LHR_RCOUNT_MSB (address = 0x31) [reset = 0x00]
      25. 8.6.25 Register LHR_OFFSET_LSB (address = 0x32) [reset = 0x00]
      26. 8.6.26 Register LHR_OFFSET_MSB (address = 0x33) [reset = 0x00]
      27. 8.6.27 Register LHR_CONFIG (address = 0x34) [reset = 0x00]
      28. 8.6.28 Register LHR_DATA_LSB (address = 0x38) [reset = 0x00]
      29. 8.6.29 Register LHR_DATA_MID (address = 0x39) [reset = 0x00]
      30. 8.6.30 Register LHR_DATA_MSB (address = 0x3A) [reset = 0x00]
      31. 8.6.31 Register LHR_STATUS (address = 0x3B) [reset = 0x00]
      32. 8.6.32 Register RID (address = 0x3E) [reset = 0x02]
      33. 8.6.33 Register DEVICE_ID (address = 0x3F) [reset = 0xD4]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Theory of Operation
      2. 9.1.2  RP+L Mode Calculations
      3. 9.1.3  LDC1101 RP Configuration
      4. 9.1.4  Setting Internal Time Constant 1
      5. 9.1.5  Setting Internal Time Constant 2
      6. 9.1.6  MIN_FREQ and Watchdog Configuration
      7. 9.1.7  RP+L Sample Rate Configuration with RESP_TIME
      8. 9.1.8  High Resolution Inductance Calculation (LHR mode)
      9. 9.1.9  LHR Sample Rate Configuration with RCOUNT
      10. 9.1.10 Setting RPMIN for LHR Measurements
      11. 9.1.11 Sensor Input Divider
      12. 9.1.12 Reference Clock Input
      13. 9.1.13 INTB Reporting on SDO
      14. 9.1.14 DRDY (Data Ready) Reporting on SDO
      15. 9.1.15 Comparator Functionality
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Configuration for RP+L Measurement with an Example Sensor
        2. 9.2.2.2 Device Configuration for LHR Measurement with an Example Sensor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Power Planes
      2. 11.1.2 CLKIN Routing
      3. 11.1.3 Capacitor Placement
      4. 11.1.4 Sensor Connections
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

10 Power Supply Recommendations

A parallel set of 1 µF and 0.1 µF capacitors should be used to bypass VDD, although it may be necessary to include a larger capacitor with systems which have a larger amount of supply variation. The smallest value capacitor should be placed as close as possible to the VDD pin. A ground plane is recommended to connect both the ground and the Die Attach Pad (DAP).

CLDO capacitor should be nonpolarized and have an equivalent series resistance (ESR) less than 1 Ω, with a SRF of at least 24 MHz.
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