11.1.1 Ground and Power Planes

Ground and power planes are helpful for maintaining a clean supply to the LDC1101. In the layout shown in Figure 61, a top-layer ground fill is also used for improved grounding.

11.1.2 CLKIN Routing

The CLKIN pin routing should maintain consistent impedance; typically this is 50Ω, but can be adjusted based on board geometries. If a parallel termination resistor is used, it should be placed as close as possible to the CLKIN pin. Minimize layer changes and routing through vias for the CLKIN signal. Maintain an uninterrupted ground plane under the trace.

11.1.3 Capacitor Placement

The capacitor C_LDO should be placed as close as possible to the CLDO pin.

Place the bypass capacitors as close as possible to the VDD pin, with the smaller valued capacitor placed closer.

11.1.4 Sensor Connections

The sensor capacitor should be as close as possible to the sensor inductor. The INA and INB traces should be routed in parallel and as close as possible to each other to minimize coupling of noise. If cable is to be used, then INA and INB should be a twisted pair or in coaxial cable. The distance between the INA/INB pins and the sensor will affect the maximum possible sensor frequency. For some applications, it may be helpful to place small value capacitor (for example, 10 pF) from INA to ground and INB to ground; these capacitors should be located close to the INA and INB pins.

Refer to Application Note LDC Sensor Design (SNOA930) for additional information on sensor design.