The void under the TPS65982 is used to via out I/O and for thermal relief vias. A minimum of 6 vias must be used for thermal dissipation to the GND planes. The thermal relief vias must be placed on the right side of the device by the power path. Figure 12-15 shows the recommended placement of the vias. Note the areas under the void where vias are not placed. This is done to allow the external FET gate drive and sense pins to route under the TPS65982 through an inner layer. Figure 12-16 shows the top layer GND pour to connect the vias and GND balls together.