米6体育平台手机版

ZHCSDU0F May 2015 – March 2022 TUSB320

PRODUCTION DATA

6.6 Timing Requirements

		MIN	MAX	UNIT
I²C (SDA, SCL)
t_SU:DAT	Data setup time	100		ns
t_HD;DAT	Data hold time	10		ns
t_SU:STA	Set-up time, SCL to start condition	0.6		µs
t_HD:STA	Hold time, (repeated) start condition to SCL	0.6		µs
t_SU:STO	Set up time for stop condition	0.6		µs
t_BUF	Bus free time between a stop and start condition	1.3		µs
t_VD;DAT	Data valid time		0.9	ns
t_VD;ACK	Data valid acknowledge time		0.9	ns
f_SCL	SCL clock frequency; I²C mode for local I²C control		400	kHz
t_r	Rise time of both SDA and SCL signals		300	ns
t_f	Fall time of both SDA and SCL signals		300	ns
C_{bus_100kHz}	Total capacitive load for each bus line when operating at ≤ 100 kHz		400	pF
C_{bus_400kHz}	Total capacitive load for each bus line when operating at ≤ 400 kHz		100	pF