9.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the Dual Mode^[1] DisplayPort inputs and outputs are high impedance. It is critical to transition the OE input from a low level to a high level after the V_CC supply has reached the minimum recommended operating voltage. Achieve this transition by a control signal to the OE input, or by an external capacitor connected between OE and GND. To ensure that the SNx5DP159 device is properly reset, the OE pin must be de-asserted for at least 100-μs before being asserted. When OE is toggled in this manner the device is reset. This requires the device to be reprogrammed if it was originally programmed through I²C for configuration. When implementing the external capacitor, the size of the external capacitor depends on the power-up ramp of the V_CC supply, where a slower ramp-up results in a larger value external capacitor. Refer to the latest reference schematic for SNx5DP159; consider approximately 200-nF capacitor as a reasonable first estimate for the size of the external capacitor. Both OE implementations are shown in Figure 20 and Figure 21.

SPACE

Figure 20. External Capacitor Controlled OE

Figure 21. OE Input from Active Controller