For this example, select LMK03328 from the device list when using PLLatinum Sim. The reference must be manually entered as 25 MHz according to input frequency requirements. Enter the desired output frequency and click Calculate Loop Filter.

From the simulation page of the PLLatinum Sim, PLL R and M dividers are set to 1, doublers are disabled. and the N divider is set to 200 to maximize the phase detector frequencies. This results in a VCO frequency of 5 GHz . The tool also tries to select maximum possible value for the PLL post dividers and for this example, the post divider is set to 8. At this point the design meets all input and output frequency requirements and designing a loop for the system and simulating performance on the clock outputs is possible.