The primary and secondary references each have a frequency doubler that can be enabled by programming R57.4 = 1 for the primary reference and R72.4 = 1 for the secondary reference. Enabling the doubler allows a higher comparison frequency for the PLL and results in a 3-dB reduction in the in-band phase noise of the LMK03328 outputs. However, enabling the doubler poses the requirement of less than 0.5% duty cycle distortion of the reference input to minimize high spurious signals in the LMK03328 outputs. If the reference input duty cycle requirement is not met, the higher order loop filter components (R3 and C3) for each PLL can be used to suppress the reference input spurs.