Each output can be configured as AC-LVPECL, AC-LVDS, AC-CML, HCSL, or LVCMOS by programming R31, R32, R34, R35, R37, R39, R41, and R43. Each output has the option to be muted or not, in case the source that sent the output becomes invalid, by programming R22. An invalid source can be either a primary or secondary reference that is no longer present, or a PLL that is unlocked. When outputs are to be muted, R20 and R21 must each be programmed to 0xFF. Outputs 0 and 1 share an output supply (VDDO_01), as well as outputs 2 and 3 (VDDO_23). Outputs 4, 5, 6, and 7 have individual output supplies (VDDO_4, VDDO_5, VDDO_6, VDDO_7). Each output supply can be independently set to 1.8 V, 2.5 V, or 3.3 V. When a particular output is desired to be disabled, the bits [5:0] in the corresponding output control register (R31, R32, R34, R35, R37, R39, R41, or R43) must be set to 0x00. If any of outputs 4, 5, 6, and 7 and the output dividers are disabled, the corresponding supplies can be connected to GND.

The AC-LVDS, AC-CML, and AC-LVPECL output structure is given in Figure 8-22 where the tail currents can be programmed to either 4 mA, 6 mA, or 8 mA to generate output voltage swings that are compatible with LVDS, CML, or LVPECL, respectively. Because this output structure is GND referenced, the output supplies can be operated from 1.8 V, 2.5 V, or 3.3 V, and offer lower power dissipation compared to traditional LVDS, CML, or LVPECL structures without any impact on jitter performance or other AC or DC specifications. Interfacing to LVDS, CML, or LVPECL receivers is accomplished using just an external AC-coupling capacitor for each output. No source termination is required, because the on-chip termination is automatically enabled when selecting AC-LVDS, AC-CML, or AC-LVPECL for good impedance matching to 50-Ω interconnects.

Figure 8-22 Structure of AC-LVDS, AC-CML, and AC-LVPECL Output Stage

The HCSL output structure is open-drain and can be direct coupled or AC coupled to HCSL receivers with appropriate termination scheme. This output structure supports either on-chip 50-Ω termination or off-chip 50-Ω termination. The on-chip, 50-Ω termination is provided primarily for convenience when driving short traces. In the case of driving long traces possibly through a connector, the on-chip termination must be disabled and a 50 Ω to GND termination at the receiver must be implemented. The output supplies can be operated from 1.8 V, 2.5 V, or 3.3 V without any impact on jitter performance or other AC or DC specifications.

The LVCMOS outputs on each side (P and N) can be configured individually to be complementary or in-phase or can be turned off (high output impedance). The LVCMOS outputs are always at 1.8-V logic level irrespective of the output supply. In case 3.3-V LVCMOS outputs are required, STATUS1 and/or STATUS0 can be configured as 3.3-V LVCMOS outputs.

Figure 8-23 through Figure 8-28 show recommendations for interfacing between the LMK03328 high-speed clock outputs and LVCMOS, LVPECL, LVDS, CML, and HCSL receivers, respectively.

Figure 8-23 Interfacing the LMK03328 1.8-V LVCMOS Output With 1.8-V LVCMOS Receiver

Figure 8-24 Interfacing the LMK03328 1.8-V LVCMOS Output With 3.3-V LVCMOS Receiver

Figure 8-25 Interfacing the LMK03328 AC-LVPECL Output With LVPECL Receiver

Figure 8-26 Interfacing the LMK03328 AC-LVDS Output With LVDS Receiver

Figure 8-27 Interfacing the LMK03328 AC-CML Output With CML Receiver

Figure 8-28 Interfacing the LMK03328 Output With HCSL Receiver