Each PLL has a dedicated Smart Input MUX. The input selection mode per PLL can be configured using the 3-state REFSEL pin or programmed through the I²C. The Smart Input MUX supports auto switching and manual switching using the control pin (or through a register). The Smart Input MUX is designed such that glitches created during switching in both auto and manual modes are suppressed at the MUX output.

In the automatic mode, the frequencies of both primary (PRIREF) and secondary (SECREF) input clocks must be within 2000 ppm. The input clocks can be in any phase. To minimize phase jump at the output, TI recommends to set a very low PLL loop bandwidth, R29.7 = 1, and R51.7 = 1. The output that is not muted must have the respective mute bypass bit in R20 and R21 set to 0x0 to verify that this output is available during an input switchover event. If the primary reference is unavailable, the input MUX automatically switches from the primary reference to the secondary reference. If primary reference is detected and available again, the input MUX switches back to the primary reference. When both the primary and secondary references are unavailable, the input MUX waits on secondary reference until the input MUX detects that the primary or secondary reference is available again. In the case where both the primary and secondary reference inputs are unavailable, LOS is active and the PLL outputs are automatically disabled. Figure 8-3 shows the timing diagram of an auto switch at the input MUX.

Figure 8-3 Smart Input MUX Auto Switch Mode Timing Diagram

R50[3-0] are the register bits that control the smart input MUX for PLL2 and PLL1, respectively, and these bits can be programmed through the I²C. Table 8-2 shows the input clock selection options for both PLLs that are supported through the I²C programming and REFSEL pin.

For those applications that require device start-up from a crystal on the secondary input, do a one-time-only switchover to the primary input when the input is available. When the auto switch on the smart MUXes of the PLL are enabled, R51.2 can be set to 0 to automatically disable the secondary crystal input path after the switchover to the primary input is complete. This removes coupling between the primary and secondary inputs and prevents input crosstalk components from appearing at the outputs. However, if the auto switch between the primary and secondary inputs is desired at any point of normal device operation, R51.2 must be set to 1, PLL must be set to a very low loop bandwidth, and R20, R21, and R22 must be set to 0x0 to verify minimal phase hit when the PLLs are relocked after switchover to either primary or secondary inputs. Figure 8-4 shows the flowchart of events triggered when R51.2 is set to 1 or 0.

Figure 8-4 Flowchart Describing Events When R51.2 is Set to 0 or 1