The LMK03328 includes two on-chip fractional PLLs with integrated VCOs, and each VCO supports a frequency range of 4.8 GHz to 5.4 GHz. Each PLL block has a input selection MUX, a phase frequency detector (PFD), a charge pump, an on-chip passive loop filter that only requires an external capacitor to ground, a feedback divider that can support both integer and fractional values and a delta sigma engine for spur suppression in fractional PLL mode. The universal inputs support single-ended and differential clocks in 1-MHz to 300-MHz frequencies, the secondary input can support crystals in 10-MHz to 52-MHz frequencies. When the PLLs operate with the crystal as the reference, the engineers can change the on-chip capacitor loaded on each leg of the crystal to margin the output frequencies. The combination of integer output dividers and universal output buffers then completes the device.

The PLLs are powered by on-chip low dropout (LDO), linear voltage regulators, and the regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs than the digital supplies that use a dedicated LDO. The LDOs provide isolation for the PLL from any noise in the external power supply rail that has a PSNR of better than –70 dBc at 50-kHz to 1-MHz ripple frequencies for 1.8-V output supplies, or a PSNR better than –80 dBc at 50-kHz to 1-MHz ripple frequencies for > 2.5-V output supplies. The engineer must connect each regulator capacitor pin to ground with a 10-µF capacitor to provide stability.