The 2 PLLs in LMK03328 can be configured to accommodate various input and output frequencies
either through the I2C programming interface or, in the absence of programming,
the PLL can be configured by the ROM page, EEPROM page, or register default settings
selected through the control pins. The PLLs can be configured by setting the Smart Input
MUX, Reference Divider, PLL Loop Filter, Feedback Divider, Prescaler Divider, and Output
Dividers.
For each PLL to operate in closed-loop mode, the following condition in Equation 1 must be met when using primary input or secondary input for the reference clock (FREF).
Equation 1. FVCO = (FREF/R) × D × [(INT +
NUM/DEN)/M]
where
- FVCO: PLL/VCO Frequency
- FREF: Frequency of selected reference input clock
- D: PLL input frequency doubler, 1=Disabled, 2=Enabled
- INT: PLL feedback divider integer value (12 bits, 1 to 4095)
- NUM: PLL feedback divider fractional numerator value (22 bits, 0 to 4194303)
- DEN: PLL feedback divider fractional denominator value (22 bits, 1 to 4194303)
- R: Primary reference divider value (3 bits, 1 to 8); R = 1 for secondary reference
- M: PLL reference input divider value (5 bits, 1 to 32)
where
- FVCO: PLL/VCO Frequency
- FREF: Frequency of selected reference input clock
- D: PLL input frequency doubler, 1=Disabled, 2=Enabled
- N: PLL feedback divider integer value (12 bits, 1 to 4095)
- R: Primary reference divider value (3 bits, 1 to 8); R = 1 for secondary reference
- M: PLL reference input divider value (5 bits, 1 to 32)
The output frequency is related to the PLL/VCO frequency or the reference input frequency (based on the output MUX selection) as given in Equation 2 or Equation 3.
Equation 2. FOUT = FREF when reference input clock selected by OUTMUX
Equation 3. FOUT = FVCO / (P × OUTDIV) when PLL is selected by OUTMUX
where
- OUTDIV: Output divider value (8 bits, 1 to 256)
- P: PLL post-divider value (2, 3, 4, 5, 6, 7, 8)