In this mode, the GPIO[5:0] pins allow hardware pin configuration of the PLL synthesizer, the synthesizer input clock selection, and output frequency and type selection. I²C is still enabled and the LSB of device address is set to 0x0. The GPIO pins are 2-state and are sampled and latched at POR, and the combination selects one of 64 page settings that are predefined in on-chip EEPROM. In this mode, the automatic output divider and PLL post divider synchronization is performed on either power-up or after toggling PDN. Table 8-14, Table 8-15, Table 8-16, Table 8-17 and Table 8-18 show the pre-defined ROM configurations according to the GPIO[5:0] pin settings.

The following sections show the blocks configured by the GPIO[5:0] pins.