There are six high-speed output dividers and each supports divide values of 1 to 256. Outputs 0 and 1 share an output divider, as well as outputs 2 and 3. Outputs 4, 5, 6, and 7 have individual output dividers. The divide values are programmed in R33, R36, R38, R40, R42, and R44. These output dividers also support coarse frequency margining for all output divide values greater than 8, which the engineer can enable on any output channel by setting the appropriate bit in R24 to a 1. In such a use case, a dynamic change in the output divider value through the I²C verifies that there are no glitches at the output irrespective of when the change is initiated. Depending on the VCO frequency and output divide values, as low as a 5% change can be initiated in the output frequency. An example case of coarse frequency margining on an output is shown in Figure 8-21.

Figure 8-21 Simplified Diagram for Coarse Frequency Margining