米6体育平台手机版

ZHCSE70D August 2015 – September 2017 TMDS181

PRODUCTION DATA.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Supply voltage⁽³⁾	V_CC	–0.3	4	V
Supply voltage⁽³⁾	V_DD	–0.3	1.4	V
Voltage	Main link input differential voltage (IN_Dx, IN_CLKx) I_IN = 15mA	V_CC - 0.75V	VCC + 0.3V	V
	TMDS outputs ( OUT_Dx)	–0.3	4
	HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1, PRE_SEL, EQ_SEL/A0, I2C_EN/PIN, SIG_EN, TX_TERM_CTL,	–0.3	4
	HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC, SCL_SRC	–0.3	6
Input Current I_IN	Main link input current (IN_Dx, IN_CLKx)		15	mA
	Continuous power dissipation	See Thermal Information
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage nominal value 3.3 V		3.135	3.3	3.465	V
V_DD	Supply voltage nominal value 1.2 V		1.1	1.2	1.27	V
T_CASE	Case temperature				92.7	°C
T_A	Operating free-air temperature	TMDS181	0		85	°C
T_A	Operating free-air temperature	TMDS181I	–40		85	°C
MAIN LINK DIFFERENTIAL PINS
V_{ID_PP}	Peak-to-peak input differential voltage		75		1560	mVpp
V_IC	Input common mode voltage		V_CC – 0.4		V_CC + 0.1	V
d_R	Data rate		0.25		6	Gbps
R_VSADJ	TMDS compliant swing voltage bias resistor nominal		4.5	7.06		kΩ
CONTROL PINS
V_I-DC	DC input voltage	Control pins	–0.3		3.6	V
V_IL⁽¹⁾	Low-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only				0.3	V
V_IL⁽¹⁾	Low-level input voltage at OE				0.8	V
V_IM⁽¹⁾	Mid-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only		1	1.2	1.4	V
V_IH⁽¹⁾	High-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL, OE⁽²⁾ pins only		2.6			V
V_OL	Low-level output voltage				0.4	V
V_OH	High-level output voltage		2.4			V
I_IH	High-level input current		–30		30	µA
I_IL	Low-level input current		–25		25	µA
I_OS	Short-circuit output current		–50		50	mA
I_OZ	High impedance output current				10	µA
R_OEPU	Pullup resistance on OE pin		150		250	kΩ

(1) These values are based upon a microcontroller driving the control pins. The pullup/pulldown/floating resistor configuration will set the internal bias to the proper voltage level which will not match the values shown here.

(2) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup resistor will set OE pin properly, but may have a different value than shown due to internal biasing.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		TMDS181x	UNIT
		RGZ (VQFN)
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	31.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	18.2	°C/W
R_θJB	Junction-to-board thermal resistance	8.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	8.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) Test conditions for Ψ_JB and Ψ_JT are clarified in the Semiconductor and IC Package Thermal Metrics.

6.5 Power Supply Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		TYP⁽²⁾	MAX⁽¹⁾	UNIT
P_D1⁽³⁾⁽⁴⁾	Device power dissipation (retimer operation)	OE = H, V_CC = 3.3 V/3.465 V, V_DD = 1.2 V/1.27 V IN_Dx: V_{ID_PP} = 1200 mV, 6 Gbps TMDS pattern, V_I = 3.3 V, I2C_EN/PIN = L, PRE_SEL= NC, EQ_SEL= NC, SDA_CTL/CLK_CTL = 0 V		800	900	mW
P_D2⁽³⁾⁽⁴⁾	Device power dissipation (redriver operation)	OE = H, V_CC = 3.3 V/3.465 V, V_DD = 1.2 V/1.27 V IN_Dx: V_{ID_PP} = 1200 mV, 2.97 Gbps TMDS pattern, V_I = 3.3 V, I2C_EN/PIN = L, PRE_SEL= NC, EQ_SEL= H, SDA_CTL/CLK_CTL = 0 V		500	600	mW
P_SD1⁽³⁾⁽⁴⁾⁽⁵⁾	Device power in standby	OE = H, V_CC = 3.3 V/3.465 V, V_DD = 1.2 V/1.27 V, HPD = H, No valid input signal		50	100	mW
P_SD2⁽³⁾⁽⁴⁾⁽⁵⁾	Device power in power down	OE = L, V_CC = 3.3 V/3.465 V, V_DD = 1.2 V/1.27 V		10	30	mW
I_CC1⁽³⁾⁽⁴⁾	VCC supply current (TMDS 6Gpbs retimer mode)	OE = H, V_CC = 3.3 V/3.465 V, V_DD = 1.2 V/1.27 V IN_Dx: V_{ID_PP} = 1200 mV, 6 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = NC, SDA_CTL/CLK_CTL = 0 V		131	150	mA
I_DD1⁽³⁾⁽⁴⁾	VDD supply current (TMDS 6Gpbs retimer mode)	OE = H, V_CC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V IN_Dx: V_{ID_PP} = 1200 mV, 6 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = NC, SDA_CTL/CLK_CTL = 0 V		332	350	mA
I_CC2⁽³⁾⁽⁴⁾	VCC supply current (TMDS 6Gpbs redriver mode)	OE = H, V_CC = 3.3 V/3.465 V, V_DD = 1.2 V/1.27 V IN_Dx: V_{ID_PP} = 1200 mV, 2.97 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V		92		mA
I_DD2⁽³⁾⁽⁴⁾	VDD supply current (TMDS 6Gpbs redriver mode)	OE = H, V_CC= 3.3 V/3.465 V, V_DD = 1.2 V/1.27 V IN_Dx: V_{ID_PP} = 1200 mV, 3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V		187		mA
I_SD1⁽⁵⁾	Standby current	OE = H, V_CC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V, HPD = H: No valid signal on IN_CLK	3.3 V rail⁽³⁾	6	15	mA
I_SD1⁽⁵⁾	Standby current		1.2 V rail	40	50	mA
I_SD2⁽⁵⁾	Power-down current	OE = L, V_CC = 3.3 V/3.465 V, V_DD = 1.2 V/1.27 V	3.3 V rail⁽³⁾	2	5	mA
I_SD2⁽⁵⁾	Power-down current	OE = L, V_CC = 3.3 V/3.465 V, V_DD = 1.2 V/1.27 V	1.2 V rail	3.5	15	mA

(1) The maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C temperature unless otherwise noted

(2) The typical rating is simulated at 3.3 V V_CC and 1.2 V V_DD and at 27°C temperature unless otherwise noted

(3) I_CC is a direct result of the source design as the TMDS181x integrated receive termination resistor accounts for 85 to 110 mA.

(4) I_DD is impacted by ARC usage. Connecting a 500 kΩ resistor to GND at SPDIF reduces the value by more than 20 mA

(5) The measurements were made with no active source connected.

6.6 TMDS Differential Input Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽²⁾	MAX⁽¹⁾	UNIT
D_{R_RX_DATA_RT}	TMDS data lanes data rate (Retimer Mode)		0.25		6	Gbps
D_{R_RX_DATA_RD}	TMDS data lanes data rate (Redriver Mode)		0.25		3.4	Gbps
D_{R_RX_CLK}	TMDS clock lanes clock rate		25		340	MHz
t_{RX_DUTY}	Input clock duty circle		40%	50%	60%
t_{CLK_JIT}	Input clock jitter tolerance				0.3	Tbit
t_{DATA_JIT}	Input data jitter tolerance	Test the TTP2, see Figure 12			150	ps
t_{RX_INTRA}	Input intrapair skew tolerance	Test at TTP2 when DR = 1.6 Gbps, see Figure 12	112			ps
t_{RX_INTER}	Input interpair skew tolerance				1.8	ns
E_QH(D)	Fixed EQ gain for data lane IN_D(0,1,2)n/p	EQ_SEL/A0 = H; fixed EQ gain, test at 6 Gbps		15		dB
E_QL(D)	Fixed EQ gain for data lane IN_D(0,1,2)n/p	EQ_SEL/A0 = L; fixed EQ gain, test at 6 Gbps		7.5		dB
E_QZ(D)	Adaptive EQ gain for data lane IN_D(0,1,2)n/p	EQ_SEL/A0 = NC; adaptive EQ (Retimer Mode Only)	2		15	dB
E_Q(c)	EQ gain for clock lane IN_CLKn/p	EQ_SEL/A0 = H,L,NC		3		dB
R_INT	Input differential termination impedance		85	100	115	Ω
V_ITERM	Input termination voltage	OE = H		3.3	3.465	V

(1) The maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C unless otherwise noted

(2) The typical rating is simulated at 3.3 V V_CC and 1.2 V V_DD and at 27°C unless otherwise noted

6.7 TMDS Differential Output Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽²⁾	MAX⁽¹⁾	UNIT
V_OH	Single-ended high level output voltage Data rate ≤1.65 Gbps	PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ;	V_CC – 10		V_CC + 10	V
	Single-ended high level output voltage Data rate >1.65 Gbps and <3.4 Gbps	PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ;	V_CC-200		V_CC + 10
	Single-ended high level output voltage Data rate >3.4 Gbps and < 6 Gbps⁽¹⁾	PRE_SEL = NC; TX_TERM_CTL = L; OE = H; DR = 6 Gbps; VSadj = 7.06 kΩ;	V_CC – 400		V_CC + 10
V_OL	Single-ended low level output voltage Data rate ≤1.65 Gbps	PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ;	V_CC – 600		V_CC – 400	V
	Single-ended low level output voltage Data rate >1.65 Gbps and <3.4 Gbps	PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ;	V_CC – 700		V_CC – 400
	Single-ended low level output voltage Data rate >3.4 Gbps and < 6 Gbps⁽¹⁾	PRE_SEL = NC; TX_TERM_CTL = L; OE = H; DR = 6 Gbps; VSadj = 7.06 kΩ;	V_CC – 1000		V_CC – 400
V_{SWING_DA}	Single-ended output voltage swing on data lane	PRE_SEL = NC; TX_TERM_CTL = H/NC/L; OE = H; DR = 270 Mbps/2.97/6 Gbps VSadj = 7.06 kΩ;	400	500	600	mV
V_{SWING_CLK}	Single-ended output voltage swing on clock lane	PRE_SEL = NC; TX_TERM_CTL = H; OE = H; Data rate ≤ 3.4 Gbps; VSadj = 7.06 kΩ;	400	500	600	mV
V_{SWING_CLK}	Single-ended output voltage swing on clock lane	PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; Data rate > 3.4 Gbps; VSadj = 7.06 kΩ;	200	300	400	mV
ΔV_SWING	Change in single-end output voltage swing per 100 Ω ΔVSadj			20		mV
ΔV_OCM(SS)	Change in steady state output common mode voltage between logic levels		–5		5	mV
V_OD(PP)	Output differential voltage before pre-emphasis	V_SADJ= 7.06 kΩ; PRE_SEL = NC see Figure 10	800		1200	mV
V_OD(SS)	Steady state output differential voltage	V_SADJ = 7.06 kΩ; PRE_SEL = L, see Figure 11	600		1075	mV
V_{OD_range}	Total TMDS data lanes output differential voltage for HDMI2.0. Retimer Mode Only See Figure 14	3.4 Gbps < R_bit ≤ 3.712 Gps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ;	335			mV
		3.712 Gbps < R_bit < 5.94 Gbps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ;	–19.66 × (R_bit²) + (106.74 × R_bit) + 209.58
		5.94 Gbps ≤ R_bit ≤ 6.0 Gbps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ;	150
I_OS	Short-circuit current limit	Main link output shorted to GND			50	mA
I_LEAK	Failsafe condition leakage current	V_CC = 0 V; V_DD = 0 V; TMDS Outputs pulled to 3.3 V through 50 Ω resistor;			45	μA
R_TERM	Source termination resistance for HDMI2.0		75		150	Ω

(1) The maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C unless otherwise noted

(2) The typical rating is simulated at 3.3 V V_CC and 1.2 V V_DD and at 27°C unless otherwise noted

6.8 DDC, I²C, HPD, and ARC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽²⁾	MAX⁽¹⁾	UNIT
DDC AND I²C
V_I-DC	SCL/SDA_SNK, SCL/SDA_SRC DC input voltage		–0.3		5.5	V
V_I-DC	SCL/SDA_CTL, DC input voltage		–0.3		3.6	V
V_IL	SCL/SDA_SNK, SCL/SDA_SRC Low level input voltage				0.3 x V_CC	V
V_IL	SCL/SDA_CTL Low level input voltage				0.3 x V_CC	V
V_IH	SCL/SDA_SNK, SCL/SDA_SRC high level input voltage		3			V
V_IH	SCL/SDA_CTL high level input voltage		0.7 x V_CC			V
V_OL	SCL/SDA_CTL, SCL/SDA_SRC low level output voltage	I₀ = 3 mA and V_CC > 2 V			0.4	V
V_OL	SCL/SDA_CTL, SCL/SDA_SRC low level output voltage	I₀ = 3 mA and V_CC < 2 V			0.2 x V_CC	V
f_SCL	SCL clock frequency fast I2C mode for local I2C control				400	kHz
C_bus	Total capacitive load for each bus line (DDC and local I2C pins)				400	pF
HPD
V_IH	High-level input voltage	HPD_SNK	2.1			V
V_IL	Low-level input voltage	HPD_SNK			0.8	V
V_OH	High-level output voltage	I_OH = –500 µA; HPD_SRC,	2.4		3.6	V
V_OL	Low-level output voltage	I_OL = 500 µA; HPD_SRC,	0		0.1	V
I_LEAK	Failsafe condition leakage current	V_CC = 0 V; V_DD = 0 V; HPD_SNK = 5 V;			40	μA
I_{H_HPD}	High-level input current	Device powered; V_IH = 5 V; I_{H_HPD} includes R_pdHPD resistor current			40	µA
I_{H_HPD}	High-level input current	Device powered; V_IL = 0.8 V; I_{L_HPD} includes R_pdHPD resistor current			30	µA
R_pdHPD	HPD input termination to GND	V_CC = 0 V	150	190	220	kΩ
SPDIF AND ARC
V_EL	Operating DC voltage for single mode ARC output	Test at ARC_OUT, see Figure 22	0		5	V
V_{IN_DC}	Operating DC voltage for SPDIF input				0.05	V
V_{SP_SW}	Signal amplitude of SPDIF input		0.2	0.5	0.6	V
V_ElSWING	Signal amplitude on the ARC output	Test at ARC_OUT, 55 Ω external termination resistor, see Figure 22	0.4	0.5	0.6	V
CLK_ARC	Signal frequency on ARC	Test at ARC_OUT, see Figure 22	3.687	5.645 ±0.1%	13.517	MHz
Duty cycle	Output clock duty cycle		45%	50%	55%
Data rate	SPDIF input DR		7.373	11.29	27.034	Mbps
t_EDGE	Rise/fall time for ARC output	From 10% to 90% voltage level			0.4	UI
R_{_IN_SPDIF}	Input termination resistance for SPDIF			75		Ω
R_est	Single mode output termination resistance	0.1 MHz to 128× the maximum frame rate	36	55	75	Ω

(1) The maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C unless otherwise noted

(2) The typical rating is simulated at 3.3 V V_CC and 1.2 V V_DD and at 27°C unless otherwise noted

6.9 Power-Up and Operation Timing Requirements

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
t_d1	V_DD stable before V_CC	0	200	µs
t_d2	V_DD and V_CC stable before OE assertion	100		µs
t_d3	CDR active operation after retimer mode initial		15	ms
t_d4	CDR turn off time after retimer mode de-assert		120	ns
VDD_ramp	V_DD supply ramp up requirements		100	ms
VCC_ramp	V_CC supply ramp up requirements		100	ms

(1) See Operation Timing for more information

TMDS181 TMDS181I Power_up_Timing_sllsen7.gif

Figure 1. Power-Up Timing for TMDS181

Figure 2. CDR Timing for TMDS181

6.10 TMDS Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽²⁾	MAX⁽¹⁾	UNIT
REDRIVER MODE
d_R	Data rate (redriver mode)		250		3400	Mbps
t_PLH	Propagation delay time (low to high)		250		600	ps
t_PHL	Propagation delay time (high to low)		250		800	ps
t_T1(1.4b)	Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets t_T3 for all three times.	TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; 1.48 Gbps and 2.97 Gbps data lines, 148 MHz and 297 MHz clock	75			ps
t_T3		TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; 1.48 Gbps, 2.97 Gbps	100			ps
t_{SK_INTRA}	Intra-pair output skew	Default setting for internal intra-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps; See Figure 8			40	ps
t_{SK_INTER}	Inter-pair output skew	Default setting for internal inter-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps; See Figure 8			100	ps
t_JITD1(1.4b)	Total output data jitter HDMI1.4b	DR = 2.97 Gbps, PRE_SEL = NC, EQ_SEL/A0 = NC ; . See Figure 12 at TTP3			0.2	Tbit
t_JITC1(1.4b)	Total output clock jitter	CLK = 25 MHz, 74.25 MHz, 75 MHz, 150 MHz, 297 MHz			0.25	Tbit
RETIMER MODE
d_R	Data rate (retimer mode)		0.25		6	Gbps
d_XVR	Automatic redriver to retimer crossover (when selected)	Measured with input signal applied = 200 mVpp	0.75	1	1.25	Gbps
f_CROSSOVER	Crossover frequency hysteresis			250		MHz
PLLB_W	Data retimer PLL bandwidth	Default loop bandwidth setting		0.4	1	MHz
t_ACQ	Input clock frequency detection and retimer acquisition time			180		µs
I_JT1	Input clock jitter tolerance	Tested when data rate >1.0Gbps			0.3	Tbit
t_T1(2.0)	Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets t_T3 for all three times.	TX_TERM_CTL = L; PRE_SEL = NC; 6 Gbps data lines,	45			ps
t_{T1 (1.4b)}		TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps and 2.97 Gbps data lines, 148 MHz and 297 MHz clock	75			ps
t_T3		TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data lines, 148 MHz, 297 MHz clock	100			ps
t_DCD	OUT_CLK ± duty cycle		40%	50%	60%
t_{SK_INTER}	Inter-pair output skew	Default setting for internal inter-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data lines, 148 MHz, 297 MHz clock; See Figure 8			0.2	Tch
t_{SK_INTRA}	Intra-pair output skew	Default setting for internal intra-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data lines, 148 MHz, 297 MHz clock; See Figure 8			0.15	Tbit
t_JITC1(1.4b)	Total output clock jitter	CLK = 25 MHz, 74.25 MHz, 75 MHz, 150 MHz, 297 MHz			0.25	Tbit
t_JITC1(2.0)		DR = 6 Gbps: CLK = 150 MHz			0.3	Tbit
t_JITD2	Total output data jitter See Figure 14	3.4 Gbps < R_bit ≤ 3.712 Gps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H			0.4	Tbit
		3.712 Gbps < R_bit < 5.94 Gbps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H			–0.0332R_bit² + 0.2312R_bit + 0.1998
		5.94 Gbps ≤ R_bit ≤ 6.0 Gbps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H			0.6

(1) The maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C unless otherwise noted

(2) The typical rating is simulated at 3.3 V V_CC and 1.2 V V_DD and at 27°C unless otherwise noted

6.11 HPD Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽²⁾	MAX⁽¹⁾	UNIT
t_PD(HPD)	Propagation delay from HPD_SNK to HPD_SRC; rising edge and falling edge⁽¹⁾	See Figure 16; not valid during switching time		40	120	ns
t_T(HPD)	HPD logical disconnected timeout	See Figure 17		2		ms

(1) The maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C unless otherwise noted

(2) The typical rating is simulated at 3.3 V V_CC and 1.2 V V_DD and at 27°C unless otherwise noted

6.12 DDC and I²C Switching Characteristics

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_r	Rise time of both SDA and SCL signals	V_CC = 3.3 V			300	ns
t_f	Fall time of both SDA and SCL signals				300	ns
t_HIGH	Pulse duration, SCL high		0.6			μs
t_LOW	Pulse duration, SCL low		1.3			μs
t_SU1	Setup time, SDA to SCL		100			ns
t_{ST, STA}	Setup time, SCL to start condition		0.6			μs
t_HD,STA	Hold time, start condition to SCL		0.6			μs
t_ST,STO	Setup time, SCL to stop condition		0.6			μs
t_(BUF)	Bus free time between stop and start condition		1.3			μs
t_PLH1	Propagation delay time, low-to-high-level output	Source to sink: 100kbps pattern; Cb(Sink) = 400 pF⁽¹⁾; see Figure 20		360		ns
t_PHL1	Propagation delay time, high-to-low-level output			230		ns
t_PLH2	Propagation delay time, low-to-high-level output	Sink to source: 100kbps pattern; Cb(Source) = 100 pF⁽¹⁾; see Figure 21		250		ns
t_PHL2	Propagation delay time, high-to-low-level output			200		ns

(1) Cb = total capacitance of one bus line in pF.

6.13 Typical Characteristics

Figure 3. Current vs Data Rate Redriver Mode

Figure 5. VSADJ vs VOD

Figure 4. Current vs Data Rate Retimer Mode

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Power Supply Electrical Characteristics

6.6 TMDS Differential Input Electrical Characteristics

6.7 TMDS Differential Output Electrical Characteristics

6.8 DDC, I2C, HPD, and ARC Electrical Characteristics

6.9 Power-Up and Operation Timing Requirements

6.10 TMDS Switching Characteristics

6.11 HPD Switching Characteristics

6.12 DDC and I2C Switching Characteristics

6.13 Typical Characteristics

6.8 DDC, I²C, HPD, and ARC Electrical Characteristics

6.12 DDC and I²C Switching Characteristics