The DP83867 provides configurable clock skew for the GTX_CLK and RX_CLK to optimize timing across the interface. The transmit and receive paths can be optimized independently. Both the transmit and receive path support 16 programmable RGMII delay modes through register configuration. Strap configuration can also be used to configure 8 programmable RGMII modes for both the transmit and receive paths. See Section 8.5.1 for details.

The timing paths can either be configured for Aligned mode or Shift mode. In Aligned mode, no clock skew is introduced. In Shift mode, the clock skew can be introduced in 0.5-ns increments (through strap configuration) or in 0.25-ns increments (through register configuration). Configuration of the Aligned mode or Shift mode is accomplished through the RGMII Control Register (RGMIICTL), address 0x0032. In Shift mode, the clock skew can be adjusted using the RGMII Delay Control Register (RGMIIDCTL), address 0x0086.