IEEE 802.3 specification for 1000BASE-T requires that the PHY layer be able to generate certain well defined test patterns on TX outputs. Clause 40 section 40.6.1.1.2 Test Modes describes these tests in detail. There are four test modes as well as the normal operation mode. These modes can be selected by writing to the CFG1 register (address 0x0009).

See IEEE 802.3 section 40.6.1.1.2 Test modes for more information on the nature of the test modes. The DP83867 provides a test clock synchronous to the IEEE test patterns. The test patterns are output on the MDI pins of the device and the transmit clock is output on the CLK_OUT pin.

For more information about configuring the DP83867 for IEEE 802.3 compliance testing, see the How to Configure DP838XX for Ethernet Compliance Testing application report (SNLS239).