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ZHCSEC3D October 2015 – November 2022 DP83867CS , DP83867E , DP83867IS

PRODUCTION DATA

6.1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
MAC INTERFACES (SGMII, RGMII)
TX_D3	25	I, PD	TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in RGMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D2	26	I, PD	TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in RGMII mode. It is synchronous to the transmit clock GTX_CLK.
SGMII_SIP	27	I, PD	Differential SGMII Data Input: This signal carries data from the MAC to the PHY in SGMII mode. It is synchronous to the differential SGMII clock input. This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode.
TX_D1	27	I, PD	TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in RGMII mode. It is synchronous to the transmit clock GTX_CLK.
SGMII_SIN	28	I, PD	Differential SGMII Data Input: This signal carries data from the MAC to the PHY in SGMII mode. It is synchronous to the differential SGMII clock input. This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode.
TX_D0	28	I, PD	TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in RGMII mode. It is synchronous to the transmit clock GTX_CLK.
GTX_CLK	29	I, PD	RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125 MHz.
RX_CLK	32	O	RGMII RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation: 2.5 MHz in 10-Mbps mode. 25 MHz in 100-Mbps mode. 125 MHz in 1000-Mbps mode.
SGMII_COP	33	S, O	Differential SGMII Clock Output: This signal is a continuous 625-MHz clock signal driven by the PHY in SGMII mode. This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode.
RX_D0	33	S, O, PD	RECEIVE DATA Bit 0: This signal carries data from the PHY to the MAC in RGMII mode. It is synchronous to the receive clock RX_CLK.
SGMII_CON	34	S, O, PD	Differential SGMII Clock Output: This signal is a continuous 625-MHz clock signal driven by the MAC in SGMII mode. This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode.
RX_D1	34	O, PD	RECEIVE DATA Bit 1: This signal carries data from the PHY to the MAC in RGMII mode. It is synchronous to the receive clock RX_CLK.
SGMII_SOP	35	S, O, PD	Differential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. It is synchronous to the differential SGMII clock output.
SGMII_SOP	35	S, O, PD	This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode.
RX_D2	35	S, O, PD	RECEIVE DATA Bit 2: This signal carries data from the PHY to the MAC in RGMII mode. It is synchronous to the receive clock RX_CLK.
SGMII_SON	36	S, O, PD	Differential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. It is synchronous to the differential SGMII clock output. This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode.
RX_D3	36	O, PD	RECEIVE DATA Bit 3: This signal carries data from the PHY to the MAC in RGMII mode. It is synchronous to the receive clock RX_CLK.
TX_CTRL	37	I, PD	TRANSMIT CONTROL: In RGMII mode, it combines the transmit enable and the transmit error signals of GMII mode using both clock edges.
RX_CTRL	38	S, O, PD	RECEIVE CONTROL: In RGMII mode, the receive data available and receive error are combined (RXDV_ER) using both rising and falling edges of the receive clock (RX_CLK).
GENERAL-PURPOSE I/O
GPIO_0	39	S, O, PD	General-Purpose I/O: This signal provides a multi-function configurable I/O. Refer to the GPIO_MUX_CTRL register for details.
GPIO_1	40	S, O, PD	General-Purpose I/O: This signal provides a multi-function configurable I/O. Refer to the GPIO_MUX_CTRL register for details.
MANAGEMENT INTERFACE
MDC	16	I, PD	MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input and output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz and no minimum.
MDIO	17	I/O	MANAGEMENT DATA I/O: Bidirectional management instruction and data signal that may be sourced by the management station or the PHY. This pin requires pullup resistor. The IEEE specified resistor value is 1.5 kΩ, but a 2.2 kΩ is acceptable.
INT / PWDN	44	I/O, PU	INTERRUPT / POWER DOWN: The default function of this pin is POWER DOWN. POWER DOWN: This is an Active Low Input. Asserting this signal low enables the power-down mode of operation. In this mode, the device powers down and consume minimum power. Register access is available through the Management Interface to configure and power up the device. INTERRUPT: When operating this pin as an interrupt, it is an open-drain architecture. TI recommends using an external 2.2-kΩ resistor connected to the VDDIO supply.
RESET
RESET_N	43	I, PU	RESET: The active low RESET initializes or reinitializes the DP83867. All internal registers re-initialize to their default state upon assertion of RESET. The RESET input must be held low for a minimum of 1 µs.
CLOCK INTERFACE
XI	15	I	CRYSTAL/OSCILLATOR INPUT: 25-MHz oscillator or crystal input (50 ppm)
XO	14	O	CRYSTAL OUTPUT: Second terminal for 25-MHz crystal. Must be left floating if a clock oscillator is used.
CLK_OUT	18	O	CLOCK OUTPUT: Output clock
JTAG INTERFACE
JTAG_CLK	20	I, PU	JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity.
JTAG_TDO	21	O	JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device through TDO.
JTAG_TMS	22	I, PU	JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction. TI recommends applying 3 clock cycles with JTAG_TMS high to reset the JTAG.
JTAG_TDI	23	I, PU	JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device through TDI.
LED INTERFACE
LED_2	45	S, I/O, PD	LED_2: By default, this pin indicates receive or transmit activity. Additional functionality is configurable through LEDCR1[11:8] register bits.
LED_1	46	S, I/O, PD	LED_1: By default, this pin indicates that 1000BASE-T link is established. Additional functionality is configurable through LEDCR1[7:4] register bits.
LED_0	47	S, I/O, PD	LED_0: By default, this pin indicates that link is established. Additional functionality is configurable through LEDCR1[3:0] register bits.
MEDIA DEPENDENT INTERFACE
TD_P_A	1	A	Differential Transmit and Receive Signals
TD_M_A	2	A	Differential Transmit and Receive Signals
TD_P_B	4	A	Differential Transmit and Receive Signals
TD_M_B	5	A	Differential Transmit and Receive Signals
TD_P_C	7	A	Differential Transmit and Receive Signals
TD_M_C	8	A	Differential Transmit and Receive Signals
TD_P_D	10	A	Differential Transmit and Receive Signals
TD_M_D	11	A	Differential Transmit and Receive Signals
OTHER PINS
RBIAS	12	A	Bias Resistor Connection. A 11-kΩ ±1% resistor should be connected from RBIAS to GND.
POWER AND GROUND PINS
VDDA2P5	3, 9	P	2.5-V Analog Supply (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
VDD1P0	6, 24, 31, 42	P	1-V Analog Supply (+15.5%, –5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
VDDA1P8	13, 48	P	1.8-V Analog Supply (±5%). No external supply is required for this pin. When unused, no connections should be made to this pin. For additional power savings, an external 1.8-V supply can be connected to these pins. When using an external supply, each pin requires a 1-µF and 0.1-µF capacitor to GND.
VDDIO	19, 30, 41	P	I/O Power: 1.8 V (±5%), 2.5 V (±5%) or 3.3 V (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND
GND	Die Attach Pad	P	Ground

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The definitions below define the functionality of each pin.

Type: I Input
Type: O Output
Type: I/O Input/Output
Type: PD, PU Internal Pulldown/Pullup
Type: S Configuration Pin
Type: P Power or GND
Type: A Analog pins