米6体育平台手机版

ZHCSEG3C September 2015 – July 2016 SN65DP149 , SN75DP149

PRODUCTION DATA.

8 Parameter Measurement Information

SN65DP149 SN75DP149 tim_TMDS_main_SLLSEJ2.gif

Figure 4. TMDS Main Link Test Circuit

Figure 5. Input and Output Timing Measurements

SN65DP149 SN75DP149 tim_HDMI_DVI_sink_SLLSEJ2.gif

Figure 6. HDMI and DVI Sink TMDS Output Skew Measurements

SN65DP149 SN75DP149 tim_TMDS_main_mode_SLLSEJ2.gif

Figure 7. TMDS Main Link Common Mode Measurements

Figure 8. Output Differential Waveform 0 dB De-Emphasis

SN65DP149 SN75DP149 PRE_SEL_L_sllsej2.gif

Figure 9. PRE_SEL = L for –2-dB De-Emphasis

SN65DP149 SN75DP149 alt_TMDS_output_SLLSEJ2.gif

1. The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, AC coupling cap, connector and another 1-2” of FR4. Trace width – 4 mils. 100-Ω differential impedance.

2. All jitter is measured at a BER of 10-9.

3. Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1.

4. AVCC = 3.3-V

5. RT = 50-Ω

6. The input signal from parallel bit error rate tester (BERT) does not have any pre-emphasis. Refer to Recommended Operating Conditions.

Figure 10. TMDS Output Jitter Measurement

SN65DP149 SN75DP149 gr_input_eyemask_SLLSEJ2.gif

TMDS data eye mask at connector for clock frequency over 165 MHz.

Figure 11. Input Eye Mask at TTP2

SN65DP149 SN75DP149 cir_HPD_test_SLLSEJ2.gif

Figure 12. HPD Test Circuit

SN65DP149 SN75DP149 tim_HPD_1_SLLSEJ2.gif

Figure 13. HPD Timing Diagram Number 1

SN65DP149 SN75DP149 tim_HPD_logic_to_SLLSEJ2.gif

Figure 14. HPD Logic Disconnect Timeout

SN65DP149 SN75DP149 tim_start_stop_cond_SLLSEJ2.gif

Figure 15. Start and Stop Condition Timing

SN65DP149 SN75DP149 tim_SCL_SDA_SLLSEJ2.gif

Figure 16. SCL and SDA Timing

SN65DP149 SN75DP149 tim_DDC_source2sink_SLLSEJ2.gif

Figure 17. DDC Propagation Delay – Source to Sink

SN65DP149 SN75DP149 tim_DDC_sink2source_SLLSEJ2.gif

Figure 18. DDC Propagation Delay – Sink to Source