To minimize the power consumption of customer application, TMDS171 used the dual power supply. VCC is 3.3 V with 5% range to support the I/O voltage. The VDD is 1.2 V with 1.1 V to 1.27 V range to supply the internal digital control circuit. TMDS171 operates in 3 different working states.
- o Power down Mode:
- OE = Low puts the device into its lowest power state by shutting down all function blocks.
- When OE is re-asserted the transitions from L→H will create a reset and if the device is programmed through I2C it must to be reprogrammed.
- Writing a 1 to register 09h[3].
- OE = High, HPD_SNK = Low
- Standby Mode: HPD_SNK = High but no valid clock signal detect on clock lane.
- Normal operation: Working in Redriver or Retimer
- When HPD assert, the device CDR and output will enable based on the signal detector circuit result.
- HPD_SRC = HPD_SNK in all conditions.
Table 36. Power Up and Operation Timing Requirements
| INPUTS |
STATUS |
| HPD_SNK |
OE |
SIG_EN |
IN_CLK |
Device Mode |
HPD_SRC |
IN_Dx |
SDA/
SCL_CTL |
OUT_Dx
OUT_CLK |
DDC |
ARC |
Mode |
| X |
L |
H or L |
X |
X |
H |
RX Termination On |
Disable |
High-Z |
Disabled |
Disable |
Power Down Mode |
| L |
H |
H or L |
X |
X |
L |
RX Termination On |
Active |
High-Z |
Disabled |
Disable |
Power Down Mode |
| H |
H |
H or L |
X |
X |
H |
RX Termination On |
Active |
High-Z |
Disabled |
Disable |
Power Down Mode by W 1 to 09h[3] |
| H |
H |
H |
No Valid TMDS Clock |
X |
H |
D0-D2 disabled with RX Termination On, IN_CLK Active |
Active |
High-Z |
Active |
Active |
Standby Mode
(Squelch waiting) |
| H |
H |
H or L |
No Valid TMDS Clock |
Retimer mode |
H |
D0-D2 disabled with RX Termination On, IN_CLK Active |
Active |
High-Z |
Active |
Active |
Standby Mode
(Squelch waiting) |
| H |
H |
H |
Valid TMDS Clock |
Retimer mode |
H |
RX Active |
Active |
TX Active |
Active |
Active |
Normal operation |
| H |
H |
H or L |
No Valid TMDS Clock |
Redriver mode |
H |
RX Active |
Active |
TX Active |
Active |
Active |
Normal operation |