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ZHCSEG5E October 2015 – September 2017 TMDS171

PRODUCTION DATA.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾⁽³⁾

		MIN	MAX	UNIT
Supply Voltage Range	VCC	–0.3	4	V
Supply Voltage Range	VDD	–0.3	1.4
Voltage Range	Main Link Input Differential Voltage (IN_Dx, IN_CLKx); I_IN = 15mA	V_CC - 0.75 V	V_CC + 0.3 V
	TMDS Outpus ( OUT_Dx)	–0.3	4
	HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1, PRE_SEL, EQ_SEL/A0, I2C_EN/PIN, SIG_EN, TX_TERM_CTL,	–0.3	4
	HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC, SCL_SRC	–0.3	6
Input Current I_IN	Main Link Input Differential Voltage (IN_Dx, IN_CLKx);		15	mA
Continuous power dissipation		See Thermal Information
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	Supply Voltage Nominal Value 3.3 V	3.135	3.3	3.465	V
V_DD	Supply Voltage Nominial Value 1.2 V	1.1	1.2	1.27	V
T_STG	Storage temperature	–65		150	°C
T_CASE	Case temperature			92.7	°C
T_A	Operating free-air temperature (TMDS171)	0		85	°C
T_A	Operating free-air temperature (TMDS171I)	–40		85	°C
MAIN LINK DIFFERENTIAL PINS
V_ID(PP)	Peak-to-peak input differential voltage	75		1560	mVpp
V_IC	Input Common Mode Voltage	VCC – 0.4		VCC + 0.1	V
d_R	Data rate	0.25		3.4	Gbps
R_(VSADJ)	TMDS compliant swing voltage bias resistor 1%		7.06		KΩ
CONTROL PINS
V_I(DC)	DC Input Voltage	–0.3		3.6	V
V_IL⁽¹⁾	Low-level input voltage OE			0.8	V
V_IL⁽¹⁾	Low-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only⁽¹⁾			0.3	V
V_IM⁽¹⁾	Mid-Level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only⁽¹⁾	1	1.2	1.4	V
V_IH⁽¹⁾	High-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL, OE⁽²⁾ pins only⁽¹⁾	2.6			V
V_OL	Low-level output voltage			0.4	V
V_OH	High-level output voltage	2.4			V
I_IH	High level input current	30		30	µA
I_IL	Low level input current	–25		25	µA
I_OS	Short circuit output current	–50		50	mA
I_OZ	High impedance output current			10	µA
R_(OEPU)	Pull up resistance on OE pin	150		250	KΩ

(1) These values are based upon a microcontroller driving the control pins. The pull up/down/floating resistor configuration will set control pins properly which will have a different value than shown due to internal biasing.

(2) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup resistor will set OE pin properly, but may have a different value than shown due to internal biasing.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		RGZ (QFN)	UNIT
THERMAL METRIC⁽¹⁾		48 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	31.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	18.2
R_θJB	Junction-to-board thermal resistance	8.1
ψ_JT	Junction-to-top characterization parameter	0.4
ψ_JB	Junction-to-board characterization parameter	8.1
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

The Maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C temperature. The Typical rating is simulated at 3.3 V_CC and 1.2 V V_DD and at 27°C temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
Power Supply
P_(D1)⁽¹⁾⁽²⁾	Device power Dissipation (Retimer Operation)	OE = H, V_CC = 3.3 V / 3.465 V, V_DD = 1.2 V / 1.27 V IN_Dx: VID_PP = 1200 mV, I2C_EN/PIN = L, PRE_SEL= H, EQ_CTL= H, SDA_CTL/CLK_CTL = 0 V 3.4 Gbps TMDS pattern, V_I= 3.3 V; VSADJ = 7.06 kΩ			675	875	mW
P_(D2)⁽¹⁾⁽²⁾	Device power Dissipation (Redriver Operation)				400	600	mW
P_(SD1)⁽¹⁾⁽²⁾⁽³⁾	Device power in Standby	OE = H, V_CC = 3.3 V / 3.465 V V_DD = 1.2 V / 1.27 V , HPD = H, No Valid input Signal			50	100	mW
P_(SD2)⁽¹⁾⁽²⁾⁽³⁾	Device power in PowerDown	OE = L, V_CC = 3.3 V / 3.465 V V_DD = 1.2 V / 1.27 V			10	30	mW
I_CC1⁽¹⁾⁽²⁾	V_CC Supply current (TMDS 3.4 Gpbs Retimer Mode)	OE = H, V_CC = 3.3 V / 3.465 V V_DD = 1.2 V / 1.27 V IN_Dx: VID_PP = 1200 mV, 3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H			80	140	mA
I_DD1⁽¹⁾⁽²⁾	V_DD Supply current (TMDS 3.4 Gpbs Retimer Mode)				286	325	mA
I_CC2⁽¹⁾⁽²⁾	V_CC Supply current (TMDS 3.4 Gpbs Redriver Mode)	OE = H, V_CC = 3.3 V / 3.465 V V_DD = 1.2 V / 1.27 V IN_Dx: VID_PP = 1200 mV, 3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H, SDA_CTL/CLK_CTL = 0V, SLEW_CTL = H			51		mA
I_DD2⁽¹⁾⁽²⁾	V_DD Supply current (TMDS 3.4 Gpbs Redriver Mode)				188		mA
I_(SD1)⁽³⁾	Standby current	OE = H, V_CC = 3.3 V / 3.465 V V_DD = 1.2 V / 1.27 V HPD = H: No valid signal on IN_CLK	3.3V Rail⁽¹⁾		6	15	mA
I_(SD1)⁽³⁾	Standby current		1.2V Rail		40	50	mA
I_(SD2)⁽³⁾	PowerDown current	OE = L, V_CC = 3.3 V / 3.465 V V_DD = 1.2 V / 1.27 V	3.3V Rail⁽¹⁾		2	5	mA
I_(SD2)⁽³⁾	PowerDown current	OE = L, V_CC = 3.3 V / 3.465 V V_DD = 1.2 V / 1.27 V	1.2V Rail		3.5	15	mA
TMDS Differential Input
D_{(R_RX_DATA)}	TMDS data lanes data rate			0.25		3.4	Gbps
D_{(R_RX_CLK)}	TMDS clock lanes clock rate			25		340	MHz
t_{RX_DUTY}	Input clock duty circle			40%	50%	60%
t_{CLK_JIT}	Input clock jitter tolerance					0.3	Tbit
t_{DATA_JIT}	Input data jitter tolerance	Test the TTP2 See Figure 11				150	ps
t_{RX_INTRA}	Input intra-pair skew tolerance	Test at TTP2 when DR = 1.6 Gbps See Figure 11		112			ps
t_{RX_INTER}	Input inter-pair skew tolerance					1.8	ns
E_QH(D)	Fixed EQ gain for data lane IN_D(0,1,2)n/p	EQ_SEL/A0=H; Fixed EQ gain, test at 3.4 Gbps			14		dB
E_QL(D)	Fixed EQ gain for data lane IN_D(0,1,2)n/p	EQ_SEL/A0=L; Fixed EQ gain, test at 3.4 Gbps			7.5
E_QZ(D)	Adaptive EQ gain for data lane IN_D(0,1,2)n/p	EQ_SEL/A0=NC; adaptive EQ		2		14
E_Q(C)	EQ gain for clock lane IN_CLKn/p	EQ_SEL/A0=H,LNC			0
R_(INT)	Input differential termination impedance			90	100	115	Ω
TMDS Differential Output
V_OH	Single-ended high level output voltage	PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ		V_CC - 10mV		V_CC + 10mV	V
V_OH	Single-ended high level output voltage	PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97 Gbps; VSadj = 7.06 kΩ		V_CC - 200mV		V_CC + 10mV
V_OL	Single-ended low level output voltage No Pre-emphasis, Load is 50 Ω pull ups to 3.135 V and 3.465 V	PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ		V_CC - 600mV		V_CC - 400mV
V_OL		PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97 Gbps; VSadj = 7.06 kΩ		V_CC - 700mV		V_CC - 400mV
V_{(SWING_DA)}	Single-ended output voltage swing on data lane	PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC; DR = ≤ 3.4 Gbps; VSadj = 7.06 kΩ		400	500	600	mV
V_{(SWING_CLK)}	Single-ended output voltage swing on clock lane	PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC; DR = ≤ 3.4 Gbps; VSadj = 7.06 kΩ		400	500	600
ΔV_(SWING)	Change in single-end output voltage swing per 100Ω ΔVSadj				20
ΔV_OCM(SS)	Change in steady state output common mode voltage between logic levels			–5		5
V_OD(PP)	Initial output differential voltage before steady state when pre-emphasis or de-emphasis is implemented	VSadj = 7.06 kΩ; PRE_SEL = NC, See Figure 8		800		1200
V_OD(SS)	Steady state output differential voltage	VSadj = 7.06 kΩ; PRE_SEL = L, See Figure 9		600		1075
I_OS	Short circuit current limit	Main link output shorted to GND				50	mA
I_LEAK	Failsafe condition leakage current	V_CC = 0 V; V_DD = 0 V; TMDS Outputs pulled to 3.3V through 50 Ω resistor				45	µA
R_(TERM)	Source Termination resistance			150		300	Ω
DDC and I2C
V_I-DC	SCL/SDA_SNK, SCL/SDA_SRC DC input voltage			–0.3		5.5	V
V_I-DC	SCL/SDA_CTL, DC input voltage			–0.3		3.6	V
V_IL	SCL/SDA_SNK, SCL/SDA_SRC Low level input voltage					0.3 x V_CC	V
V_IL	SCL/SDA_CTL Low level input voltage					0.3 x V_CC	V
V_IH	SCL/SDA_SNK, SCL/SDA_SRC high level input voltage			3			V
V_IH	SCL/SDA_CTL high level input voltage			0.7 x V_CC			V
V_OL	SCL/SDA_CTL, SCL/SDA_SRC low level output voltage	I_O = 3 mA and V_CC > 2 V				0.4	V
V_OL	SCL/SDA_CTL, SCL/SDA_SRC low level output voltage	I_O = 3 mA and V_CC < 2 V				0.2 x V_CC	V
f_SCL	SCL clock frequency fast I2C mode for local I2C control					400	kHz
C_bus	Total capacitive load for each bus line (DDC and local I2C pins)					400	pF
HPD
V_IH	High-level input voltage	HPD_SNK		2.1			V
V_IL	Low-level input voltage	HPD_SNK				0.8
V_OH	High-level output voltage	I_OH = -500 µA; HPD_SRC		2.4		3.6
V_OL	Low-level output voltage	I_OL = -500 µA; HPD_SRC		0		0.1
I_LEAK	Failsafe condition leakage current	V_CC = 0 V; V_DD = 0 V; HPD_SNK = 5 V				40
I_H(HPD)	High level input current	Device powered; V_IH = 5 V; I_H(HPD) includes R_pd(HPD) resistor current				40	µA
I_H(HPD)	High level input current	Device powered; V_IL = 0.8 V; I_H(HPD) includes R_pd(HPD) resistor current				30	µA
R_pd(HPD)	HPD input termination to GND;	V_CC < 0 V		150	190	220	kΩ
SPDIF and ARC
V_(EL)	Operating DC voltage for single mode ARC output	Test at ARC_OUT, see Figure 19		0		5	V
V_IN(DC)	Operating DC voltage for SPDIF input					0.05	V
V_{(SP_SW)}	Signal amplitude of SPDIF input			0.2	0.5	0.6	V
V_(ElSWING)	Signal amplitude on the ARC output	Test at ARC_OUT, 75 Ω external termination resistor, see Figure 19		0.4	0.5	0.6	V
CLK_(ARC)	Signal frequency on ARC	Test at ARC_OUT, see Figure 19		3.687	5.645±0.1%	13.517	MHz
Duty Cycle	Output Clock Duty cycle			45%	50%	55%
Data Rate	SPDIF Input DR			7.373	11.29	27.034	Mbps
t_EDGE	The rise/fall time for ARC output	From 10% to 90% voltage level, see Figure 19				0.4	UI
R_{(IN_SPDIF)}	The Input Termination resistance for SPDIF				75		Ω
R_(EST)	Single mode Output Termination resistance	0.1 MHz to 128 times the maximum frame rate		36	55	75	Ω

(1) I_CC is a direct result of the source design as the TMDS171 integrated receive termination resistor accounts for 85 mA to 100 mA.

(2) I_DD is impacted by ARC usage. Connecting a 500 KΩ resistor to GND at SPDIF reduces the value by more than 20 mA.

(3) The measurements were made with no active source connected.

6.6 Switching Characteristics

The Maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD and at 85°C temperature. The Typical rating is simulated at 3.3 V V_CC and 1.2 V V_DD and at 27°C temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TMDS Redriver Mode
D_R	Data rate (Redriver mode)		250		3400	Mbps
t_PLH	Propagation delay time (low to high)		250		600	ps
t_PHL	Propagation delay time (high to low)		250		800
t_T1	Transition time (rise and fall time); measured at 20% and 80% levels for Data Lanes.	TX_TERM_CTL=L; PRE_SEL=NC; Data Rate 3.4 Gbps; Clock 340 MHz	75
t_SK1(T)	Intra-pair output skew	TX_TERM_CTL=NC; PRE_SEL=NC;			40
t_SK2(T)	Inter-pair output skew	TX_TERM_CTL=NC; PRE_SEL=NC;			100
t_JITD1	Total output data jitter	DR = 750 Mbps, PRE_SEL = NC, EQ_SEL/A0 = NC. See Figure 5 at TTP3			0.2	Tbit
t_JITC1	Total output clock jitter				0.25	Tbit
TMDS Retimer Mode
D_R	Data rate (retimer mod )		1.2		3.4	Gbps
d_(XVR)	Automatic redriver to Retimer Cross-Over	Measured with input signal applied from 0 to 200 mV_PP	0.75	1.00	1.25	Gbps
f_(CROSSOVER)	Crossover frequency hysteresis			250		MHz
PLL_(BW)	Data Retimer PLL bandwidth	Default loop bandwidth setting		0.4	1	MHz
t_ACQ	Input Clock Frequency Detection and Retimer Acquisition Time			180		µs
I_JT1	Input Clock Jitter Tolerance	Tested when data rate > 1.0 Gbps			0.3	Tbit
t_T1	Transition time (rise and fall time); measured at 20% and 80% levels for Data Lanes. TMDS		75			ps
t_DCD	OUT_CLK ± duty cycle		40%	50%	60%
t_{SK_INTER}	Inter-pair output skew	Default setting for internal inter-pair skew adjust, PRE_SEL = NC; TX_TERM_CTL = NC, DR ≤ 3.4 Gbps; See Figure 6			0.2	Tch
t_{SK_INTRA}	Intra-pair output skew	Default setting for internal intra-pair skew adjust, PRE_SEL = NC; TX_TERM_CTL = NC, DR ≤ 3.4 Gbps; See Figure 6			0.15	Tbit
t_JITC2	Total output clock jitter	CLK Rate ≤ 340 MHz			0.25	Tbit
t_JITD2	Total output data jitter	DR ≤ 3.4 Gbps; See Figure 11			0.2	Tbit
HPD
t_PD(HPD)	Propagation delay from HPD_SNK to HPD_SRC; rising edge and falling edge⁽¹⁾	see Figure 13; not valid during switching time		40	120	ns
t_T(HPD)	HPD logical disconnected timeout	see Figure 14		2		ms
DDC and I2C
t_r	Rise time of both SDA and SCL signals	V_CC = 3.3 V			300	ns
t_f	Fall time of both SDA and SCL signals				300	ns
t_HIGH	Pulse duration, SCL high		0.6			µs
t_LOW	Pulse duration, SCL low		1.3			µs
t_SU1	Setup time, SDA to SCL		100			ns
t_ST,STA	Setup time, SCL to start condition		0.6			µs
t_HD,STA	Hold time, start condition to SCL		0.6
t_ST,STO	Setup time, SCL to stop condition		0.6
t_(BUF)	Bus free time between stop and start condition		1.3
t_PLH1	Propagation delay time, low-to-high-level output	Source to Sink:100 kbps pattern; C_b(Sink) = 400 pF⁽²⁾; see Figure 17		360		ns
t_PHL1	Propagation delay time, high-to-low-level output			230
t_PLH2	Propagation delay time, low-to-high-level output	Sink to Source: 100 kbps pattern; C_b(Source) = 100 pF⁽²⁾; see Figure 18		250
t_PHL2	Propagation delay time, high-to-low-level output			200

(1) The Maximum rating is simulated at 3.465 V V_CC and 1.27 V V_DD

(2) Cb = total capacitance of one bus line in pF.

6.7 Typical Characteristics

Figure 1. Current vs Data Rate Redriver Mode

Figure 3. V_OD vs VSadj

Figure 2. Current vs Data Rate Retimer Mode