The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. When the feedback pin voltage falls below the PG threshold voltage (V_IT(PG) + V_HYS(PG), typically 89.3%), the PG pin open-drain output engages and pulls the PG pin close to GND. When the feedback voltage exceeds the V_IT(PG) threshold by an amount greater than V_HYS(PG) (typically 91.3%), the PG pin becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. Using an external voltage detector device such as the TPS3702 is also recommended in applications where more accurate voltage monitoring or overvoltage monitoring is required.

The use of a feed-forward capacitor (C_FF) can cause glitches on start-up, and the power-good circuit may not function normally below the minimum input supply range. For more details on the use of the power-good circuitry, see the Section 8.1.14 section.