Figure 6-1 Serial Data Input Timing Diagram

There are several considerations for programming:

• A slew rate of at least 30 V/µs is recommended for the CLK, DATA, LE
• The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the last CLK signal, the data is sent from the shift registers to a register bank
• The LE pin may be held high after programming and clock pulses are ignored
• When CLK and DATA lines are shared between devices, TI recommends diving down the voltage to the CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity
• If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming