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ZHCSEV0 March 2016 DS90UB921-Q1

PRODUCTION DATA.

9 Power Supply Recommendations

9.1 Power Up Requirements and PDB Pin

When VDDIO and VDD33 are powered separately, the VDDIO supply (1.8V or 3.3V) should ramp 100us before the other supply, VDD33. If VDDIO is tied with VDD33, both supplies may ramp at the same time. The VDDs (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If the PDB pin is not controlled by a microcontroller, a large capacitor on the pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or VDD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.

A minimum low pulse of 2ms is required when toggling the PDB pin to perform a hard reset.

All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.

Figure 32. Timing Diagram of DS90UB921-Q1

Table 9. Power-Up Sequencing Constraints

Symbol	Description	Test Conditions	Min	Max	Units
VDDIO	VDDIO voltage range		3.0	3.6	V
VDDIO	VDDIO voltage range		1.71	1.89	V
VDD33	VDD33 voltage range		3.0	3.6	V
V_{PDB_LOW}	PDB LOW threshold Note: V_PDBshould not exceed limit for respective I/O voltage before 90% voltage of VDD12	VDDIO = 3.3V ± 10%	0.8		V
V_{PDB_HIGH}	PDB HIGH threshold	VDDIO = 3.3V ± 10%		2.0	V
t₀	VDDIO rise time	These time constants are specified for rise time of power supply voltage ramp (10% - 90%)	0.05	<1.5	ms
t₃	VDD33 rise time	These time constants are specified for rise time of power supply voltage ramp (10% - 90%)	0.05	<1.5	ms
t₁	VDD33 delay time	V_IL of rising edge (VDDIO) to V_IL of rising edge (VDD33) The power supplies may be ramped simultaneously. If sequenced, VDDIO should be first..	>0		ms
t₄	Startup time	The part is powered up after the startup time has elapsed from the moment PDB goes HIGH. Local I2C is available to read/write 921 registers after this time.		<1	ms

This device is designed to operate from an input core voltage supply of 3.3V. Some devices provide separate power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.

9.2 CML Interconnect Guidelines

See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.

Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
- – S = space between the pair
- – 2S = space between pairs
- – 3S = space to LVCMOS signal
Minimize the number of Vias
Use differential connectors when operating above 500 Mbps line speed
Maintain balance of the traces
Minimize skew within the pair

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas Instruments web site at: www.ti.com/lvds.