米6体育平台手机版

ZHCSFB4A July 2016 – January 2024 DS90UB964-Q1

PRODUCTION DATA

4.9 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS	PIN OR FREQUENCY	MIN	TYP	MAX	UNIT
HSTX DRIVER
HSTX_DBR	Data rate		CSI0_D[3:0]P/N CSI1_D[3:0]P/N	400	800	1600	Mbps
fCLK	DDR Clock frequency		CSI0_CLKP/N CSI1_CLKP/N	200	400	800	MHz
ΔV_CMTX(HF)	Common mode voltage variations HF	Above 450MHz	CSI0_D0P/N CSI0_D1P/N CSI0_D2P/N CSI0_D3P/N CSI0_CLKP/N CSI1_D0P/N CSI1_D1P/N CSI1_D2P/N CSI1_D3P/N CSI1_CLKP/N			15	mV_RMS
ΔV_CMTX(LF)	Common mode voltage variations LF	Between 50 and 450MHz				25	mV_RMS
t_RHS t_FHS	20% to 80% Rise and Fall HS	HS data rates ≤ 1Gbps (UI ≥ 1ns)				0.3	UI
		HS data rates > 1Gbps (UI ≤ 1ns) but less than 1.5Gbps (UI ≥ 0.667ns)				0.35	UI
		Applicable when supporting maximum HS data rates ≤ 1.5Gbps.		100			ps
		Applicable for all HS data rates when supporting > 1.5Gbps.				0.4	UI
		Applicable for all HS data rates when supporting > 1.5Gbps.		50			ps
SDD_TX	TX differential return loss	f_LPMAX	HS data rates <1.5Gbps			-18	dB
		f_H				-9	dB
		f_MAX				-3	dB
		f_LPMAX	HS data rates >1.5Gbps			-18	dB
		f_H				-4.5	dB
		f_MAX				-2.5	dB
LPTX DRIVER
t_RLP	Rise Time LP⁽¹⁾	15% to 85% rise time	CSI0_D0P/N CSI0_D1P/N CSI0_D2P/N CSI0_D3P/N CSI1_D0P/N CSI1_D1P/N CSI1_D2P/N CSI1_D3P/N CSI0_CLKP/N CSI1_CLKP/N			25	ns
t_FLP	Fall Time LP ⁽¹⁾	15% to 85% fall time				25	ns
t_REOT	Rise Time Post-EoT⁽¹⁾	30%-85% rise time				35	ns
t_LP-PULSE-TX	Pulse width of the LP exclusive-OR clock⁽¹⁾	First LP exclusive-OR clock pulse after Stop state or last pulse before Stop state		40			ns
t_LP-PULSE-TX	Pulse width of the LP exclusive-OR clock⁽¹⁾	All other pulses		20			ns
t_LP-PER-TX	Period of the LP exclusive-OR clock			90			ns
DV/DtSR	Slew rate ⁽¹⁾	C_LOAD = 0 pF				500	mV/ns
		C_LOAD = 5 pF				300	mV/ns
		C_LOAD = 20 pF				250	mV/ns
		C_LOAD = 70 pF				150	mV/ns
		C_LOAD = 0 to 70 pF (Falling Edge Only)		30			mV/ns
		C_LOAD = 0 to 70 pF (Rising Edge Only)		30			mV/ns
		C_LOAD = 0 to 70 pF (Rising Edge Only) ⁽²⁾⁽³⁾		30 - 0.075×(VO,INST - 700)			mV/ns
		C_LOAD = 0 to 70 pF (Rising Edge Only) ⁽⁴⁾⁽⁵⁾		25 - 0.0625×(VO,INST - 500)			mV/ns
C_LOAD	Load capacitance⁽¹⁾			0		70	pF
CSI-2 TIMING SPECIFICATIONS — DATA-CLOCK TIMING (Figure 4-6, Figure 4-7)
UI_INST	UI instantaneous	In 1, 2, 3, or 4 Lane Configuration HS Data rate = 400 Mbps	CSI0_D0P/N CSI0_D1P/N CSI0_D2P/N CSI0_D3P/N CSI1_D0P/N CSI1_D1P/N CSI1_D2P/N CSI1_D3P/N CSI0_CLKP/N CSI1_CLKP/N		2.5		ns
		In 1, 2, 3, or 4 Lane Configuration HS Data rate = 800 Mbps			1.25		ns
		In 1, 2, 3, or 4 Lane Configuration HS Data rate = 1.6Gbps			0.625		ns
ΔUI	UI variation	UI ≥ 1ns (Figure 4-5)		-10%		10%	UI
ΔUI	UI variation	UI < 1ns (Figure 4-5)		-5%		5%	UI
t_SKEW(TX)	Data to Clock Skew (measured at transmitter) Skew between clock and data from ideal center	HS Data rate ≤ 1Gbps (Figure 4-5)		-0.15		0.15	UI_INST
t_SKEW(TX)		1Gbps ≤ HS Data rate ≤ 1.5Gbps (Figure 4-5)		-0.2		0.2	UI_INST
t_SKEW(TX) static	Static Data to Clock Skew	HS Data rate > 1.5Gbps		-0.2		0.2	UI_INST
t_SKEW(TX) dynamic	Dynamic Data to Clock Skew	HS Data rate > 1.5Gbps		-0.15		0.15	UI_INST
CSI-2 TIMING SPECIFICATIONS - GLOBAL OPERATION (Figure 4-6, Figure 4-7)
t_CLK-POST	HS exit		CSI0_D0P/N CSI0_D1P/N CSI0_D2P/N CSI0_D3P/N CSI1_D0P/N CSI1_D1P/N CSI1_D2P/N CSI1_D3P/N CSI0_CLKP/N CSI1_CLKP/N	60 + 52×UI_INST			ns
t_CLK-PRE	Time HS clock shall be driver prior to any associated Data Lane beginning the transition from LP to HS mode			8			UI_INST
t_CLK-PREPARE	Clock Lane HS Entry			38		95	ns
t_CLK-SETTLE	Time interval during which the HS receiver shall ignore any Clock Lane HS transitions			95		300	ns
t_CLK-TERM-EN	Time-out at Clock Lane Display Module to enable HS Termination			Time for Dn to reach VTERM-EN		38	ns
t_CLK-TRAIL	Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst			60			ns
t_CLK-PREPARE + t_CLK-ZERO	TCLK-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock			300			ns
t_D-TERM-EN	Time for the Data Lane receiver to enable the HS line termination			Time for Dn to reach V-TERM-EN		35 + 4×UI_INST	ns
t_EOT	Transmitted time interval from the start of t_HS-TRAIL to the start of the LP-11 state following a HS burst					105 + 12×UI_INST	ns
t_HS-EXIT	Time that the transmitter drives LP=11 following a HS burst			100			ns
t_HS-PREPARE	Data Lane HS Entry			40 + 4×UI_INST		85 + 6×UI_INST	ns
t_HS-PREPARE + t_HS-ZERO	t_HS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence			145 + 10×UI_INST			ns
t_HS-SETTLE	Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of t_HS-SETTLE			85 + 6×UI_INST		145 + 10×UI_INST	ns
t_HS-SKIP	Time interval during which the HS-RX should ignore any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst.			40		55 + 4×UI_INST	ns
t_HS-TRAIL	Data Lane HS Exit			60 + 4×UI_INST			ns
t_LPX	Transmitted length of LP state			50			ns
t_WAKEUP	Recovery Time from Ultra Low Power State (ULPS)			1			ms

(1) C_LOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be <10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2ns delay.

(2) When the output voltage is between 700 mV and 930 mV

(3) Applicable when the supported data rate ≤ 1.5Gbps

(4) When the output voltage is between 550 mV and 790 mV

(5) Applicable when the supported data rate > 1.5Gbps.