ZHCSFB4A July 2016 – January 2024 DS90UB964-Q1
PRODUCTION DATA
The PDB pin is active HIGH and must remain LOW while the VDD pin power supplies are in transition. An external RC network on the PDB pin can be connected so PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDD18, a 10kΩ pullup and a > 10μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until both power supplies have reached steady state.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PDB | ||||||
tLRST | PDB Reset Low Pulse | 2 | ms |