The AEQ process steps through the allowed equalizer control values to find a value that allows the Clock Data Recovery (CDR) circuit to keep a valid lock condition. The circuit waits for a programmed re-lock time period for each EQ setting, then the circuit checks the results for a valid lock. If a valid lock is detected, the circuit stops at the current EQ setting and maintains a constant value as long as the lock state persists. If the deserializer loses the lock, the adaptive equalizer resumes the LOCK algorithm and the EQ setting is incremented to the next valid state. When the lock is lost, the circuit searches the EQ settings to find another valid setting to reacquire the serial data stream sent by the serializer that remains locked. TI recommends setting LINK_ERROR_COUNT_EN and LINK_SFIL_WAIT to 1 in Register 0xB9 to increase link robustness.