The FPD-Link III BIST is configured and enabled by programming the BIST Control register. Set 0xB3 = 0x01 to enable BIST and set 0xB3 = 00 to disable BIST. BIST pass or fail status can be brought to GPIO pins by selecting the Pass indication for each receive port using the GPIOx_PIN_CTL registers. The Pass/Fail status is de-asserted low for each data error detected on the selected port input data. In addition, the Receiver Lock status for selected ports can be brought out to the GPIO pins as well. After completion of BIST, the BIST Error Counter can be read to determine if errors occurred during the test. If the DS90UB964-Q1 failed to lock to the input signal or lost lock to the input signal, the BIST Error Counter indicates 0xFF. The maximum normal count value is 0xFE. The SER_BIST_ACT register bit 0xD0[5] can be monitored during testing to make sure BIST is activated in the serializer.

During BIST, DS90UB964-Q1 output activity are gated by BIST_Control[7:6] (BIST_OUT_MODE[1:0]) as follows:

00 : Outputs disabled during BIST

10 : Outputs enabled during BIST

When enabling the outputs by setting BIST_OUT_MODE = 10, the CSI-2 is inactive by default (LP11 state). To exercise the CSI-2 interface during BIST mode, the Pattern Generator can be enabled to send a video data pattern on the CSI-2 outputs.

The BIST clock frequency is controlled by the BIST_CLOCK_SOURCE field in the BIST Control register. This 2-bit value is written to the Serializer register 0x14[2:1]. A value of 00 selects an external clock. A non-zero value enables an internal clock of the frequency defined in the Serializer register 0x14. The BIST_CLOCK_SOURCE field is sampled at the start of BIST. Changing this value after BIST is enabled does not change operation.