The DS90UB964-Q1 implements two I2C-compatible serial control buses. Both I2C ports support local device configuration and incorporate a bidirectional control channel (BCC) that allows communication with a remote serializers as well as remote I2C target devices.

The device address is set through a resistor divider connected to the IDx pin (R1 and R2 – see Figure 5-21).

Figure 5-21 Serial Control Bus Connection

The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to V_I2C, where V_I2C is a voltage rail that matches the voltage applied to VDDIO. The pull-up resistor value can be adjusted to account for capacitive loading and data rate requirements. Refer to "I2C Bus Pullup Resistor Calculation" (SLVA689) to determine the pull-up resistor value to V_I2C. The signals are either pulled High, or driven Low.

The IDX pin configures the control interface to one of eight possible device addresses. A pullup resistor and a pulldown resistor can be used to set the appropriate voltage ratio between the IDX input pin (V_IDX) and V_(VDD18), each ratio corresponding to a specific device address. See Table 5-13, Serial Control Bus Addresses for IDX.

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions Low while SCL is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See Figure 5-22.

Figure 5-22 START and STOP Conditions

To communicate with a remote device, the host controller sends the target address and listens for a response from the target. This response is referred to as an acknowledge bit (ACK). If a target on the bus is addressed correctly, the target acknowledges (ACKs) the controller by driving the SDA bus low. If the address does not match one of the target addresses of the device, the target not-acknowledges (NACKs) the controller by letting SDA be pulled High. ACKs can also occur on the bus when data transmissions are in process. When the controller is writing data, the target ACKs after every data byte is successfully received. When the controller is reading data, the controller ACKs after every data byte is received to let the target know the controller wants to receive another data byte. When the controller wants to stop reading, the controller NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 5-23 and a WRITE is shown in Figure 5-24.

Figure 5-23 Serial Control Bus — READ

Figure 5-24 Serial Control Bus — WRITE

Figure 5-25 Basic Operation

The I2C Controller located at the Deserializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, refer to I2C Communication Over FPD-Link III With Bidirectional Control Channel (SNLA131) and I2C over DS90UB913/4 FPD-Link III With Bidirectional Control Channel (SNLA222).