ZHCSFB4A July   2016  – January 2024 DS90UB964-Q1

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings – JEDEC
    3. 4.3  ESD Ratings – IEC and ISO
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Thermal Information
    6. 4.6  DC Electrical Characteristics
    7. 4.7  AC Electrical Characteristics
    8. 4.8  Recommended Timing for the Serial Control Bus
    9. 4.9  AC Electrical Characteristics
    10. 4.10 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1  RAW Data Type Support and Rates
      2. 5.4.2  MODE Pin
      3. 5.4.3  REFCLK
      4. 5.4.4  Receiver Port Control
      5. 5.4.5  Input Jitter Tolerance
      6. 5.4.6  Adaptive Equalizer
        1. 5.4.6.1 Channel Requirements
        2. 5.4.6.2 Adaptive Equalizer Algorithm
        3. 5.4.6.3 AEQ Settings
          1. 5.4.6.3.1 AEQ Start-Up and Initialization
          2. 5.4.6.3.2 AEQ Range
          3. 5.4.6.3.3 AEQ Timing
          4. 5.4.6.3.4 AEQ Threshold
      7. 5.4.7  Channel Monitor Loop-Through Output Driver
        1. 5.4.7.1 Code Example for CMLOUT FPD3 RX Port 0:
      8. 5.4.8  RX Port Status
        1. 5.4.8.1 RX Parity Status
        2. 5.4.8.2 FPD-Link Decoder Status
        3. 5.4.8.3 RX Port Input Signal Detection
      9. 5.4.9  GPIO Support
        1. 5.4.9.1 GPIO Input Control and Status
        2. 5.4.9.2 GPIO Output Pin Control
        3. 5.4.9.3 Back Channel GPIO
        4. 5.4.9.4 GPIO Pin Status
        5. 5.4.9.5 Other GPIO Pin Controls
      10. 5.4.10 RAW Mode LV / FV Controls
      11. 5.4.11 Video Stream Forwarding
      12. 5.4.12 CSI-2 Protocol Layer
      13. 5.4.13 CSI-2 Short Packet
      14. 5.4.14 CSI-2 Long Packet
      15. 5.4.15 CSI-2 Data Identifier
      16. 5.4.16 Virtual Channel and Context
      17. 5.4.17 CSI-2 Mode Virtual Channel Mapping
        1. 5.4.17.1 Example 1
        2. 5.4.17.2 Example 2
      18. 5.4.18 CSI-2 Transmitter Frequency
      19. 5.4.19 CSI-2 Transmitter Status
      20. 5.4.20 Video Buffers
      21. 5.4.21 CSI-2 Line Count and Line Length
      22. 5.4.22 FrameSync Operation
        1. 5.4.22.1 External FrameSync Control
        2. 5.4.22.2 Internally Generated FrameSync
          1. 5.4.22.2.1 Code Example for Internally Generated FrameSync
      23. 5.4.23 CSI-2 Forwarding
        1. 5.4.23.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 5.4.23.2 Synchronized CSI-2 Forwarding
        3. 5.4.23.3 Basic Synchronized CSI-2 Forwarding
          1. 5.4.23.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 5.4.23.4 Line-Interleaved CSI-2 Forwarding
          1. 5.4.23.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 5.4.23.5 Line-Concatenated CSI-2 Forwarding
          1. 5.4.23.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 5.4.23.6 CSI-2 Replicate Mode
        7. 5.4.23.7 CSI-2 Transmitter Output Control
        8. 5.4.23.8 Enabling and Disabling CSI-2 Transmitters
    5. 5.5 Programming
      1. 5.5.1  Serial Control Bus
      2. 5.5.2  Second I2C Port
      3. 5.5.3  I2C Target Operation
      4. 5.5.4  Remote Target Operation
      5. 5.5.5  Remote Target Addressing
      6. 5.5.6  Broadcast Write to Remote Devices
        1. 5.5.6.1 Code Example for Broadcast Write
      7. 5.5.7  I2C Proxy Controller
      8. 5.5.8  I2C Proxy Controller Timing
        1. 5.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 5.5.9  Interrupt Support
        1. 5.5.9.1 Code Example to Enable Interrupts
        2. 5.5.9.2 FPD-Link III Receive Port Interrupts
        3. 5.5.9.3 Code Example to Readback Interrupts
        4. 5.5.9.4 CSI-2 Transmit Port Interrupts
      10. 5.5.10 Timestamp – Video Skew Detection
      11. 5.5.11 Pattern Generation
        1. 5.5.11.1 Reference Color Bar Pattern
        2. 5.5.11.2 Fixed Color Patterns
        3. 5.5.11.3 Pattern Generator Programming
          1. 5.5.11.3.1 Determining Color Bar Size
        4. 5.5.11.4 Code Example for Pattern Generator
      12. 5.5.12 FPD-Link BIST Mode
        1. 5.5.12.1 BIST Operation
    6. 5.6 Register Maps
      1. 5.6.1 Main_Page Registers
      2. 5.6.2 Indirect Access Registers
        1. 5.6.2.1 PATGEN_And_CSI-2 Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power-Over-Coax
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 VDD Power Supply
      2. 6.4.2 Power-Up Sequencing
        1. 6.4.2.1 PDB Pin
    5. 6.5 Layout
      1. 6.5.1 Layout Guidelines
        1. 6.5.1.1 Ground
        2. 6.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 6.5.1.3 CSI-2 Guidelines
      2. 6.5.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 支持资源
    4. 7.4 Trademarks
    5. 7.5 静电放电警告
    6. 7.6 术语表
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

8 Revision History

Changes from Revision * (July 2016) to Revision A (December 2023)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 通篇更正了拼写错误和格式小问题Go
  • 更新了数据表格式Go
  • 更新了典型应用原理图，以清楚地显示两个 CSI-2 输出端口Go
  • Updated I2C pull-up resistor recommendationsGo
  • Updated Legend for Pin Functions TableGo
  • Moved INTB pin description to OTHERS categoryGo
  • Renamed Pin 4 to RESGo
  • Updated VDD pin descriptionsGo
  • Updated REFCLK pin descriptionGo
  • Updated input current specification to include internal pulldowns for GPIO and PDB pins Go
  • Updated VIH and VIL specifications for PDB and REFCLK pinsGo
  • Added VIN specificationGo
  • Updated VID specificationGo
  • Changed input jitter symbol from IJT to TIJIT and renamed Input Jitter Tolerance parameter to Input Jitter to be consistent with specifying max input jitterGo
  • Removed the tCLK_MISS specification from the CSI-2 Timing Specifications tableGo
  • Updated VID diagramGo
  • Added information about the bidirectional control channelGo
  • Corrected serializer part numbers throughout data sheetGo
  • Renamed section to RAW Data Type Support & Rates for clarityGo
  • Added information about YUV supportGo
  • Added information about FPD-Link line ratesGo
  • Removed mentions of Coaxial or STP mode since device automatically accepts either configuration regardless of MODE strapGo
  • Updated resistor values while keeping the same voltage ratioGo
  • Rewrote target voltage range in terms of V(VDD18) Go
  • Clarified default back channel rateGo
  • Clarified that the REFCLK value can range between 23MHz to 25MHz throughout the documentGo
  • Added section on receiver port controlGo
  • Added a channel requirements section to the data sheetGo
  • Updated AEQ section and register 0xB9 register setting recommendation for clarityGo
  • Added additional AEQ sections for clarityGo
  • Fixed spelling errors throughout the documentGo
  • Added sections related to the RX port status for clarityGo
  • Added additional GPIO sections on input and output controlGo
  • Added additional information on back channel GPIOGo
  • Added section on video stream forwardingGo
  • Added information about YUV and RAW8 support Go
  • Added information about conversion from DVP format to CSI-2 data packetsGo
  • Updated VC-ID mapping example graphicsGo
  • Added section on CSI-2 Transmitter Status for clarityGo
  • Added note about how to program the FS_HIGH_TIME registerGo
  • Clarified that CSI-2 forwarding must be disabled before CSI-2 replicate mode is enabledGo
  • Added section on enabling and disabling CSI-2 transmittersGo
  • Added additional I2C sections to clarify functionalityGo
  • Changed I2C terminology to "Controller" and "Target"Go
  • Added a sentence to clarify that VI2C must match the voltage applied to VDDIOGo
  • Reworded the Serial Control Bus section to reference VI2C instead of VDDIOGo
  • Updated resistor values while keeping the same voltage ratioGo
  • Rewrote target voltage range in terms of VVDD18 Go
  • Clarified that Register 0x01 (RESET_CTL) can only be written by the primary I2C portGo
  • Added additional information about how to configure a broadcast write to remote devicesGo
  • Removed unnecessary register writes in the Code Example for Broadcast WriteGo
  • Clarified instructions for how to configure Pattern Generation on the CSI-2 PortGo
  • Updated Pattern Generator example script to update data type to RAW10Go
  • Renamed section to FPD-Link BIST ModeGo
  • Added additional information about BISTGo
  • Renamed section to BIST OperationGo
  • Added additional information about BIST operationGo
  • Removed all RESERVED registers from the data sheetGo
  • Updated the description of register bit 0x34[1]Go
  • Made register 0x41 publicGo
  • Updated the description of register bits 0x42[6:4]Go
  • Updated the description of register bit 0x4E[1] to clarify functionalityGo
  • RESERVED register 0x6D[2] as the bit is no longer applicableGo
  • Corrected default value of register bit 0x7C[5]Go
  • RESERVED value of register bit 0x7D[6]Go
  • Removed RESERVED indirect register pages in the description of register bits 0xB0[5:2]Go
  • Updated the description of register bits 0xB3[2:1]Go
  • Made register bits 0xB6[5:3] publicGo
  • Updated the description of register bits 0xB9[3:0]Go
  • Corrected default value of register bit 0xD2[2]Go
  • Updated name of register 0xD2Go
  • Updated the name of Indirect Register Page 0 to PATGEN_AND_CSI-2Go
  • Added additional information about PoCGo
  • Added 2G PoC network exampleGo
  • Updated typical connection diagram to include a reference to App Note SLVA689Go
  • Removed optional 10 kΩ pulldown resistor on Pin 4 in the Typical Connection DiagramGo
  • Highlighted HW and SW control options on PDB pinGo
  • Added pin numbers to Typical Application DiagramGo
  • Added additional CSI-2 diagrams for Start of Transmission and End of TransmissionGo
  • Updated power-up sequencing diagram and tableGo
  • Added additional layout section for clarityGo
  • Updated MIPI CSI-2 D-PHY layout recommendationsGo
  • Updated layout exampleGo
  • Added additional related documentationGo
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