9.1.1 Loop Filter

Each PLL of the LMK04208 requires a dedicated loop filter.

Figure 21. PLL1 and PLL2 Loop Filters

9.1.2 Driving CLKin and OSCin Inputs

9.1.2.1 Driving CLKin Pins with a Differential Source

Both CLKin ports can be driven by differential signals. TI recommends that the input mode be set to bipolar (CLKinX_BUF_TYPE = 0) when using differential reference clocks. The LMK04208 internally biases the input pins so the differential interface should be AC coupled. The recommended circuits for driving the CLKin pins with either LVDS or LVPECL are shown in Figure 22 and Figure 23.

Figure 22. CLKinX/X* Termination for an LVDS Reference Clock Source

Figure 23. CLKinX/X* Termination for an LVPECL Reference Clock Source

Finally, a reference clock source that produces a differential sine wave output can drive the CLKin pins using the following circuit. Note: the signal level must conform to the requirements for the CLKin pins listed in Electrical Characteristics.

Figure 24. CLKinX/X* Termination for a Differential Sinewave Reference Clock Source

9.1.2.2 Driving CLKin Pins with a Single-Ended Source

The CLKin pins of the LMK04208 can be driven using a single-ended reference clock source, for example, either a sine wave source or an LVCMOS/LVTTL source. Either AC coupling or DC coupling may be used. In the case of the sine wave source that is expecting a 50-Ω load, TI recommends that AC coupling be used as shown in Figure 25 with a 50-Ω termination.

NOTE

The signal level must conform to the requirements for the CLKin pins listed in Electrical Characteristics. CLKinX_BUF_TYPE in Register 11 is recommended to be set to bipolar mode (CLKinX_BUF_TYPE = 0).

Figure 25. CLKinX/X* Single-Ended Termination

If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC coupling may be used. If DC coupling is used, the CLKinX_BUF_TYPE should be set to MOS buffer mode (CLKinX_BUF_TYPE = 1) and the voltage swing of the source must meet the specifications for DC coupled, MOS-mode clock inputs given in the table of Electrical Characteristics. If AC coupling is used, the CLKinX_BUF_TYPE should be set to the bipolar buffer mode (CLKinX_BUF_TYPE = 0). The voltage swing at the input pins must meet the specifications for AC coupled, bipolar mode clock inputs given in the table of Electrical Characteristics. In this case, some attenuation of the clock input level may be required. A simple resistive divider circuit before the AC coupling capacitor is sufficient.

Figure 26. DC Coupled LVCMOS/LVTTL Reference Clock

9.1.3 Termination and Use of Clock Output (Drivers)

When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:

• Transmission line theory should be followed for good impedance matching to prevent reflections.
• Clock drivers should be presented with the proper loads. For example:
  • LVDS drivers are current drivers and require a closed current loop.
  • LVPECL drivers are open emitters and require a DC path to ground.
• Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level. In this case, the signal should normally be AC coupled.

It is possible to drive a non-LVPECL or non-LVDS receiver with an LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode voltage). For example, when driving the OSCin/OSCin* input of the LMK04208 , OSCin/OSCin* should be AC coupled because OSCin/OSCin* biases the signal to the proper DC level (See Figure 40) This is only slightly different from the AC coupled cases described in Driving CLKin Pins with a Single-Ended Source because the DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains the same. The receiver (OSCin/OSCin*) sets the input to the optimum DC bias voltage (common mode voltage), not the driver.

9.1.3.1 Termination for DC Coupled Differential Operation

For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS receiver as shown in Figure 27.

Figure 27. Differential LVDS Operation, DC Coupling, No Biasing of the Receiver

For DC coupled operation of an LVPECL driver, terminate with 50 Ω to V_CC - 2 V as shown in Figure 28. Alternatively, terminate with a Thevenin equivalent circuit (120-Ω resistor connected to V_CC and an 82-Ω resistor connected to ground with the driver connected to the junction of the 120-Ω and 82-Ω resistors) as shown in Figure 29 for V_CC = 3.3 V.

Figure 28. Differential LVPECL Operation, DC Coupling

Figure 29. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent

9.1.3.2 Termination for AC Coupled Differential Operation

AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important to ensure the receiver is biased to its ideal DC level.

When driving non-biased LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors, however the proper DC bias point needs to be established at the receiver. One way to do this is with the termination circuitry in Figure 30.

Figure 30. Differential LVDS Operation, AC Coupling,
External Biasing at the Receiver

Some LVDS receivers may have internal biasing on the inputs. In this case, the circuit shown in Figure 30 is modified by replacing the 50-Ω terminations to Vbias with a single 100-Ω resistor across the input pins of the receiver, as shown in Figure 31. When using AC coupling with LVDS outputs, there may be a startup delay observed in the clock output due to capacitor charging. The previous figures employ a 0.10-µF capacitor. This value may need to be adjusted to meet the startup requirements for a particular application.

Figure 31. LVDS Termination for a Self-Biased Receiver

LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120-Ω emitter resistors close to the LVPECL driver to provide a DC path to ground as shown in Figure 32. For proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical DC bias voltage for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82-Ω resistor connected to V_CC and a 120-Ω resistor connected to ground with the driver connected to the junction of the 82-Ω and 120-Ω resistors) is a valid termination as shown in Figure 32 for V_CC = 3.3 V. Note this Thevenin circuit is different from the DC coupled example in Figure 29.

Figure 32. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent,
External Biasing at the Receiver

9.1.3.3 Termination for Single-Ended Operation

A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal.

It is possible to use an LVPECL driver as one or two separate 800 mVpp signals. When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminate the unused driver. When DC coupling one of the LMK04208 clock LVPECL drivers, the termination should be 50 Ω to V_CC - 2 V as shown in Figure 33. The Thevenin equivalent circuit is also a valid termination as shown in Figure 34 for Vcc = 3.3 V.

Figure 33. Single-Ended LVPECL Operation, DC Coupling

Figure 34. Single-Ended LVPECL Operation, DC Coupling,
Thevenin Equivalent

When AC coupling an LVPECL driver use a 120-Ω emitter resistor to provide a DC path to ground and ensure a 50-Ω termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL receivers is 2 V (See Driving CLKin Pins with a Single-Ended Source). If the companion driver is not used it should be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF test equipment no DC bias point (0 VDC) is required for safe and proper operation. The internal 50-Ω termination of the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 35.

Figure 35. Single-Ended LVPECL Operation, AC Coupling

9.1.4 Frequency Planning with the LMK04208

Calculating the value of the output dividers for use with the LMK04208 is simple due to the architecture of the LMK04208. That is, the VCO divider may be bypassed and the clock output dividers allow for even and odd output divide values from 2 to 1045. For most applications, TI recommends bypassing the VCO divider.

The procedure for determining the needed LMK04208 device and clock output divider values for a set of clock output frequencies is straightforward.

1. Calculate the least common multiple (LCM) of the clock output frequencies.
2. Determine which VCO ranges will support the target clock output frequencies given the LCM.
3. Determine the clock output divide values based on VCO frequency.
4. Determine the PLL2_P, PLL2_N, and PLL2_R divider values given the OSCin VCXO or crystal frequency and VCO frequency.

For example, given the following target output frequencies: 200 MHz, 120 MHz, and 25 MHz with a VCXO frequency of 40 MHz:

• First determine the LCM of the three frequencies. LCM(200 MHz, 120 MHz, 25 MHz) = 600 MHz. The LCM frequency is the lowest frequency for which all of the target output frequencies are integer divisors of the LCM. Note: if there is one frequency which causes the LCM to be very large, greater than 3 GHz for example, determine if there is a single frequency requirement which causes this. It may be possible to select the VCXO/crystal frequency to satisfy this frequency requirement through OSCout or CLKout3/4 driven by OSCin. In this way it is possible to get non-integer related frequencies at the outputs.
• Second, since the LCM is not in a VCO frequency range supported by the LMK04208, multiply the LCM frequency by an integer which causes it to fall into a valid VCO frequency range of an LMK04208 device. In this case 600 MHz * 5 = 3000 MHz which is valid for the LMK04208.
• Third, continuing the example by using a VCO frequency of 3000 MHz and the LMK04208, the CLKout dividers can be calculated by simply dividing the VCO frequency by the output frequency. To output 200 MHz, 120 MHz, and 25 MHz the output dividers will be 12, 20, and 96 respectively.
  • 3000 MHz / 200 MHz = 15
  • 3000 MHz / 120 MHz = 25
  • 3000 MHz / 25 MHz = 120
• Fourth, PLL2 must be locked to its input reference. Refer to PLL Programming for more information on this topic. By programming the clock output dividers and the PLL2 dividers the VCO can lock to the frequency of 3000 MHz and the clock outputs dividers will each divide the VCO frequency down to the target output frequencies of 200 MHz, 120 MHz, and 25 MHz.

Refer to AN-1865, Frequency Synthesis and Planning for PLL Architectures for more information on this topic and LCM calculations.

9.1.5 PLL Programming

To lock a PLL the divided reference and divided feedback from VCO or VCXO must result in the same phase detector frequency. The tables below illustrate how the divides are structured for the reference path (R) and feedback path (N) depending on the MODE of the device.

9.1.6 Digital Lock Detect Frequency Accuracy

The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback signals of the PLL for each event to occur. When a PLL digital lock event occurs the PLL's digital lock detect is asserted true. When the holdover exit event occurs, the device will exit holdover mode.

For a digital lock detect event to occur there must be a “lock count” number of phase detector cycles of PLLX during which the time/phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the user programmable "window size." Since there must be at least "lock count" phase detector events before a lock event occurs, a minimum digital lock event time can be calculated as "lock count" / f_PDX where X = 1 for PLL1 or 2 for PLL2.

By using Equation 5, values for a "lock count" and "window size" can be chosen to set the frequency accuracy required by the system in ppm before the digital lock detect event occurs:

Equation 5.

The effect of the "lock count" value is that it shortens the effective lock window size by dividing the "window size" by "lock count".

If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by "window size", then the “lock count” value is reset to 0.

9.1.7 Calculating Dynamic Digital Delay Values for Any Divide

This section explains how to calculate the dynamic digital delay for any divide value.

Dynamic digital delay allows the time offset between two or more clock outputs to be adjusted with no or minimal interruption of clock outputs. Since the clock outputs are operating at a known frequency, the time offset can also be expressed as a phase shift. When dynamically adjusting the digital delay of clock outputs with different frequencies the phase shift should be expressed in terms of the higher frequency clock. The step size of the smallest time adjustment possible is equal to half the period of the Clock Distribution Path, which is the VCO frequency (Equation 3) or the VCO frequency divided by the VCO divider (Equation 4) if not bypassed. The smallest degree phase adjustment with respect to a clock frequency will be 360 * the smallest time adjustment * the clock frequency. The total number of phase offsets that the LMK04208 is able to achieve using dynamic digital delay is equal 1 / (higher clock frequency * the smallest phase adjustment).

Equation 7 calculates the digital delay value that must be programmed for a synchronizing clock to achieve a 0 time/phase offset from the qualifying clock. Once this digital delay value is known, it is possible to calculate the digital delay value for any phase offset. The qualifying clock for dynamic digital delay is selected by the FEEDBACK_MUX. When dynamic digital delay is engaged with same clock output used for the qualifying clock and the new synchronized clock, it is termed relative dynamic digital delay since causing another SYNC event with the same digital delay value will offset the clock by the same phase once again. The important part of relative dynamic digital delay is that the CLKoutX_HS must be programmed correctly when the SYNC event occurs (Table 6). This can result in needing to program the device twice. Once to set the new CLKoutX_DDLY with CLKoutX_HS as required for the SYNC event, and again to set the CLKoutX_HS to its desired value.

Digital delay values are programmed using the CLKoutX_DDLY and CLKoutX_HS registers as shown in Equation 8. For example, to achieve a digital delay of 13.5, program CLKoutX_DDLY = 14 and CLKoutX_HS = 1.

Equation 7.

Equation 7 uses the ceiling operator. To find the ceiling of a fractional number round up. An integer remains the same value.

Note: since the digital delay value for 0 time/phase offset is a function of the qualifying clock's divide value, the resulting digital delay value can be used for any clock output operating at any frequency to achieve a 0 time/phase offset from the qualifying clock. Therefore the calculated time shift table will also be the same as in Table 115.

9.1.8 Optional Crystal Oscillator Implementation (OSCin/OSCin*)

The LMK04208 features supporting circuitry for a discretely implemented oscillator driving the OSCin port pins. Figure 36 illustrates a reference design circuit for a crystal oscillator:

Figure 36. Reference Design Circuit for Crystal Oscillator Option

This circuit topology represents a parallel resonant mode oscillator design. When selecting a crystal for parallel resonance, the total load capacitance, C_L, must be specified. The load capacitance is the sum of the tuning capacitance (C_TUNE), the capacitance seen looking into the OSCin port (C_IN), and stray capacitance due to PCB parasitics (C_STRAY), and is given by Equation 9.

Equation 9.

C_TUNE is provided by the varactor diode shown in Figure 36, Skyworks model SMV1249-074LF. A dual diode package with common cathode provides the variable capacitance for tuning. The single diode capacitance ranges from approximately 31 pF at 0.3 V to 3.4 pF at 3 V. The capacitance range of the dual package (anode to anode) is approximately 15.5 pF at 3 V to 1.7 pF at 0.3 V. The desired value of V_TUNE applied to the diode should be V_CC/2, or 1.65 V for V_CC = 3.3 V. The typical performance curve from the data sheet for the SMV1249-074LF indicates that the capacitance at this voltage is approximately 6 pF (12 pF / 2).

The nominal input capacitance (C_IN) of the LMK04208 OSCin pins is 6 pF. The stray capacitance (C_STRAY) of the PCB should be minimized by arranging the oscillator circuit layout to achieve trace lengths as short as possible and as narrow as possible trace width (50 Ω characteristic impedance is not required).

As an example, assume that C_STRAY is 4 pF. The total load capacitance is nominally:

Equation 10.

Consequently the load capacitance specification for the crystal in this case should be nominally 14 pF.

The 2.2-nF capacitors shown in the circuit are coupling capacitors that block the DC tuning voltage applied by the 4.7-kΩ and 10-kΩ resistors. The value of these coupling capacitors should be large, relative to the value of C_TUNE (C_C1 = C_C2 >> C_TUNE), so that C_TUNE becomes the dominant capacitance.

For a specific value of C_L, the corresponding resonant frequency (F_L) of the parallel resonant mode circuit is:

Equation 11.

where

• F_S = Series resonant frequency
• C₁ = Motional capacitance of the crystal
• C_L = Load capacitance
• C₀ = Shunt capacitance of the crystal, specified on the crystal datasheet

The normalized tuning range of the circuit is closely approximated by:

Equation 12.

C_L1, C_L2 = The endpoints of the circuit’s load capacitance range, assuming a variable capacitance element is one component of the load. F_CL1, F_CL2 = parallel resonant frequencies at the extremes of the circuit’s load capacitance range.

A common range for the pullability ratio, C₀/C₁, is 250 to 280. The ratio of the load capacitance to the shunt capacitance is ~(n * 1000), n < 10. Hence, picking a crystal with a smaller pullability ratio supports a wider tuning range because this allows the scale factors related to the load capacitance to dominate.

9.1.8.1 Examples of Phase Noise and Jitter Performance

Examples of the phase noise and jitter performance of the LMK04208 with a crystal oscillator are shown in Table 116. This table illustrates the clock output phase noise when a 20.48-MHz crystal is paired with PLL1. Performance of other LMK04208 devices will be similar.

Table 116. Example RMS Jitter and Clock Output Phase Noise for LMK04208
with a 20.48 MHz Crystal Driving OSCin (T = 25 °C, V_CC = 3.3 V) ⁽¹⁾

INTEGRATION BANDWIDTH	CLOCK OUTPUT TYPE	PLL2 PDF = 20.48 MHz (EN_PLL2_REF2X = 0, XTAL_LVL = 3)	PLL2 PDF = 40.96 MHz (EN_PLL2_REF2X = 1, XTAL_LVL = 3)
		fCLK = 245.76 MHz	fCLK = 122.88 MHz	fCLK = 245.76 MHz
RMS JITTER (fs, RMS)
100 Hz – 20 MHz	LVCMOS	374	412	382
	LVDS	419	421	372
	LVPECL 1.6 Vpp	460	448	440
10 kHz – 20 MHz	LVCMOS	226	195	190
	LVDS	231	205	194
	LVPECL 1.6 Vpp	226	191	188
PHASE NOISE (dBc/Hz)
Offset	Clock Output Type	PLL2 PDF = 20.48 MHz (EN_PLL2_REF2X = 0, XTAL_LVL = 3)	PLL2 PDF = 40.96 MHz (EN_PLL2_REF2X = 1, XTAL_LVL = 3)
		fCLK = 245.76 MHz	fCLK = 122.88 MHz	fCLK = 245.76 MHz
100 Hz	LVCMOS	-87	-93	-87
	LVDS	-86	-91	-86
	LVPECL 1.6 Vpp	-86	-92	-85
1 kHz	LVCMOS	-115	-121	-115
	LVDS	-115	-123	-116
	LVPECL 1.6 Vpp	-114	-122	-116
10 kHz	LVCMOS	-117	-128	-122
	LVDS	-117	-128	-122
	LVPECL 1.6 Vpp	-117	-128	-122
100 kHz	LVCMOS	-130	-135	-129
	LVDS	-130	-135	-129
	LVPECL 1.6 Vpp	-129	-135	-129
1 MHz	LVCMOS	-150	-154	-148
	LVDS	-149	-153	-148
	LVPECL 1.6 Vpp	-150	-154	-148
40 MHz	LVCMOS	-159	-162	-159
	LVDS	-157	-159	-157
	LVPECL 1.6 Vpp	-159	-161	-159

(1) Performance data and crystal specifications contained in this section are based on Vectron model VXB1-1150-20M480, 20.48 MHz. PLL1 has a narrow loop bandwidth, PLL2 loop parameters are: C1 = 150 pF, C2 = 120 nF, R2 = 470 Ω, Charge Pump current = 3.2 mA, Phase detector frequency = 20.48 MHz or 40.96 MHz, VCO frequency = 2949.12 MHz. Loop filter was optimized for 40.96 MHz phase detector performance.

Example crystal specifications are presented in Table 117.

Table 117. Example Crystal Specifications

PARAMETER	VALUE
Nominal Frequency (MHz)	20.48
Frequency Stability, T = 25 °C	± 10 ppm
Operating temperature range	-40 °C to +85 °C
Frequency Stability, -40 °C to +85 °C	± 15 ppm
Load Capacitance	14 pF
Shunt Capacitance (C0)	5 pF Maximum
Motional Capacitance (C1)	20 fF ± 30%
Equivalent Series Resistance	25 Ω Maximum
Drive level	2 mWatts Maximum
C0/C1 ratio	225 typical, 250 Maximum

See Figure 37 for a representative tuning curve.

Figure 37. Example Tuning Curve, 20.48-MHz Crystal

The tuning curve achieved in the user's application may differ from the curve shown above due to differences in PCB layout and component selection.

This data is measured on the bench with the crystal integrated with the LMK04208. Using a voltmeter to monitor the V_TUNE node for the crystal, the PLL1 reference clock input frequency is swept in frequency and the resulting tuning voltage generated by PLL1 is measured at each frequency. At each value of the reference clock frequency, the lock state of PLL1 should be monitored to ensure that the tuning voltage applied to the crystal is valid.

The curve shows over the tuning voltage range of 0.3 VDC to 3.0 VDC, the frequency range is -140 to +91 ppm; or equivalently, a tuning range of -2850 Hz to +1850 Hz. The measured tuning voltage at the nominal crystal frequency (20.48 MHz) is 1.7 V. Using the diode data sheet tuning characteristics, this voltage results in a tuning capacitance of approximately 6.5 pF.

The tuning curve data can be used to calculate the gain of the oscillator (K_VCO). The data used in the calculations is taken from the most linear portion of the curve, a region centered on the crossover point at the nominal frequency (20.48 MHz). For a well designed circuit, this is the most likely operating range. In this case, the tuning range used for the calculations is ± 1000 Hz (± 0.001 MHz), or ± 81.4 ppm. The simplest method is to calculate the ratio:

Equation 13.

ΔF2 and ΔF1 are in units of MHz. Using data from the curve this becomes:

Equation 14.

A second method uses the tuning data in units of ppm:

Equation 15.

F_NOM is the nominal frequency of the crystal and is in units of MHz. Using the data, this becomes:

Equation 16.

In order to ensure startup of the oscillator circuit, the equivalent series resistance (ESR) of the selected crystal should conform to the specifications listed in the table of Electrical Characteristics.

It is also important to select a crystal with adequate power dissipation capability, or drive level. If the drive level supplied by the oscillator exceeds the maximum specified by the crystal manufacturer, the crystal will undergo excessive aging and possibly become damaged. Drive level is directly proportional to resonant frequency, capacitive load seen by the crystal, voltage and equivalent series resistance (ESR).

For more complete coverage of crystal oscillator design, see:

Clocks and Timers or AN-1939 Crystal Based Oscillator Design with the LMK04000 Family.

9.2.1 Design Requirements

Given a remote radio head (RRU) type application which needs to clock some ADCs, DACs, FPGA, SERDES, and an LO. The input clock will be a recovered clock which needs jitter cleaning. The FPGA clock should have a clock output on power up. A summary of clock input and output requirements are as follows:

Clock Input:

• 30.72-MHz recovered clock.

Clock Outputs:

• 1x 245.76-MHz clock for ADC, LVPECL
• 2x 983.04-MHz clock for DAC, LVPECL
• 1x 122.88-MHz clock for FPGA, LVDS. POR clock
• 1x 122.88-MHz clock for SERDES, LVPECL
• 2x 122.88-MHz clock for LO, LVCMOS

It is also desirable to have the holdover feature engage if the recovered clock reference is ever lost. The following information reviews the steps to produce this design.

9.2.2 Detailed Design Procedure

Design of all aspects of the LMK04208 are quite involved and software has been written to assist in part selection, part programming, loop filter design, and simulation. This design procedure will give a quick outline of the process.

Note that this information is current as of the date of the release of this datasheet. Design tools receive continuous improvements to add features and improve model accuracy. Refer to software instructions or training for latest features.

1. Device Selection
   • the key to device selection is required VCO frequency given required output frequencies. The device must be able to produce the VCO frequency that can be divided down to required output frequencies.
   • The software design tools will take into account VCO frequency range for specific devices based on the application's required output frequencies. Using an external VCO provides increased flexibility regarding valid designs.
   • To understand the process better, refer to Frequency Planning with the LMK04208 for more detail on calculating valid VCO frequency when using integer dividers using the least common multiple (LCM) of the output frequencies.
2. Device Configuration
   • There are many possible permutations of dividers and other registers to get same input and output frequencies from a device. However there are some optimizations and trade-offs to be considered.
     • If more than one divider is in series, for instance VCO divider to CLKout divider, or VCO divider to PLL prescaler to PLL N. It is possible although not assured that some crosstalk/mixing could be created when using some divides.
   • The design software normally attempts to maximize phase detector frequency, use smallest dividers, and maximizes PLL charge pump current.
   • When an external VCXO or crystal is used for jitter cleaning, the design software will choose the maximum frequency value, depending on design software options, this max frequency may be limited to standard value VCXOs/Crystals. Note, depending on application, different frequency VCXOs may be chosen to generate some of the required output frequencies.
   • Refer to PLL Programming for divider equations need to ensure PLL is locked. The design software is able to configure the device for most cases, but at this time for advanced features like 0-delay, the user must take care to ensure proper PLL programming.
   • These guidelines may be followed when configuring PLL related dividers or other related registers:
     • For lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide value.
     • For lowest possible in-band PLL flat noise, maximize charge pump current. The highest value charge pump currents often have similar performance due to diminishing returns.
     • To reduce loop filter component sizes, increase N value and/or reduce charge pump current.
     • Large capacitors help reduce phase detector spurs at phase detector frequency caused by external VCOs/VCXOs with low input impedance.
     • As rule of thumb, keeping the phase detector frequency approximately between 10 * PLL loop bandwidth and 100 * PLL loop bandwidth. A phase detector frequency less than 5 * PLL bandwidth may be unstable and a phase detector frequency > 100 * loop bandwidth may experience increased lock time due to cycle slipping. However for clock generation/jitter cleaning applications, lock time is typically not critical and large phase detector frequencies typically result in reduced PLL noise, so cycle-slipping during lock is acceptable.
3. PLL Loop Filter Design
   • TI recommends using Clock Architect to design your loop filter.
   • Best loop filter design and simulation can be achieved when:
     • Custom reference and VCXO phase noise profiles are loaded into the software.
     • VCO gain of the external VCXO or possible external VCO device are entered.
   • The design tool will return solutions with high reference/phase detector frequencies and high charge pump currents by default. It is possible to reduce the phase detector frequency charge pump current in Clock Architect. Due to the narrow loop bandwidth used on PLL1, it is common to lower the phase detector frequency and/or charge pump current on PLL1 to reduce component size.
   • While designing loop filter, adjusting the charge pump current or N value can help with loop filter component selection. Lower charge pump currents and larger N values result in smaller component values but may increase impacts of leakage and reduce PLL phase noise performance.
   • More detailed understanding of loop filter design can found in Dean Banerjee's PLL Performance, Simulation, and Design (www.ti.com/tool/pll_book).
4. Clock Output Assignment
   • At this time the design software does not take into account frequency assignment to specific outputs except to ensure that the output frequencies can be achieved. It is best to consider proximity of each clock output to each other and other PLL circuitry when choosing final clock output locations. Here are some guidelines to help achieve best performance when assigning outputs to specific CLKout/OSCout pins.
     • Group common frequencies together.
     • PLL charge pump circuitry can cause crosstalk at charge pump frequency. Place outputs sharing charge pump frequency or lower priority outputs not sensitive to charge pump frequency spurs together.
     • Muxes can create a path for noise coupling. Consider all frequencies which may have some bleed through from non-selected mux inputs.
       • For example, LMK04208 CLKout3 and CLKout4 share a mux with OSCin.
   • Some clock targets require low close-in phase noise. If possible, use a VCXO based PLL1 output from CLKout3 or CLKout4 for such a clock target. An example is a clock to a PLL reference.
   • Some clock targets require excellent noise floor performance. Outputs driven by the internal VCO have the best noise floor performance. An example is an ADC or DAC.
5. Other device specific configuration. For LMK04208, consider the following:
   • PLL lock time based on programming:
     • In addition to the time it takes the device to lock to frequency, there is a digital filter to avoid false lock time detects which can also be used to ensure a specific PPM frequency accuracy. This also impacts the time it takes for the digital lock detect (DLD) pin to be asserted. Refer to Digital Lock Detect Frequency Accuracy for more information.
   • Holdover configuration:
     • Specific PPM frequency accuracy required to exit holdover can be programmed. Refer to Digital Lock Detect Frequency Accuracy for more information.
   • Digital delay: phase alignment of the output clocks.
   • Analog delay: another method to shift phases of clocks with finer resolution with the penalty of increase noise floor.
   • Dynamic digital delay: ability to shift phase alignment of clocks with minimum disruption during operation.
6. Device Programming
   • The software tool TICS Pro for EVM programming can be used to setup the device in the desired configuration, then export a hex register map suitable for use in application.

Some additional information on each part of the design procedure for the RRU example is below.

9.2.3 Application Curve

Figure 39. LVPECL Phase Noise, 122.88 MHz
Illustration of Different Performance Depending on Signal Path

9.3.1 System Level Diagram

Figure 40 and Figure 41 show an LMK04208 device with external circuitry for clocking and for power supply to serve as a guideline for good practices when designing with the LMK04208. Refer to Pin Connection Recommendations for more details on the pin connections and bypassing recommendations. Also refer to the evaluation board in LMK0480x Evaluation Board Instructions. PCB design will also play a role in device performance. As discussed in PLL LO Reference , the LO clocks at 122.88 MHz may be moved to CLKout5 if the VCXO frequency will support 122.88 MHz output.

Figure 40. Example Application – System Schematic Except for Power

Figure 40 shows the primary reference clock input is at CLKin0/0*. A secondary reference clock is driving CLKin1/1*. Both clocks are depicted as AC coupled drivers. The VCXO attached to the OSCin/OSCin* port is configured as an AC coupled single-ended driver. Any of the input ports (CLKin0/0*, CLKin1/1*, or OSCin/OSCin*) may be configured as either differential or single-ended. These options are discussed later in the data sheet.

See Loop Filter for more information on PLL1 and PLL2 loop filters.

In the system shown in Figure 40, LVPECL clocks are AC coupled via 0.1 µF capacitors and LVDS clocks are DC coupled. Some clock outputs are depicted as LVPECL with 240-Ω emitter resistors and some clock outputs as LVDS. The appropriate output termination on each output should be implemented according to the output format to be programmed by the user. Later sections of this data sheet illustrate alternative methods for AC coupling, DC coupling, and terminating the clock outputs. PCB design will influence crosstalk performance. Tightly coupled clock traces will have less crosstalk than loosely coupled clock traces. Also proximity to other clocks traces will influence crosstalk.

Figure 41. Example Application – Power System Schematic

Figure 41 shows an example decoupling and bypassing scheme for the LMK04208, which could apply to configuration shown in Figure 40. The ferrite beads and capacitors drawn in dotted lines are optional (see Pin Connection Recommendations). Two power planes are used in these example designs, one for the clock outputs and one for PLL circuits. It is possible to reduce the number of decoupling components by tying together clock output Vcc pins for CLKouts that share the same frequency or otherwise can tolerate potential crosstalk between outputs with different frequencies. In the two examples, Vcc2 and Vcc3 can be tied together since CLKout1 and CLKout2 will operate at the same frequencies. Vcc10, Vcc11, and Vcc12 can be tied together since potential crosstalk between the FPGA/SerDes clocks and low-frequency synchronization clocks will not impact the performance of these digital interfaces, which typically have less stringent jitter requirements. PCB design will influence impedance to the supply. Vias and traces will increase the impedance to the power supply. Ensure good direct return current paths.

9.4.1 LVCMOS Complementary vs. Non-Complementary Operation

• TI recommends using a complementary LVCMOS output format such as LVCMOS (Norm/Inv) to reduce switching noise and crosstalk when using LVCMOS.
• If only a single LVCMOS output is required, the complementary LVCMOS output format can still be used by leaving the unused LVCMOS output floating.
• A non-complimentary format such as LVCMOS (Norm/Norm) is not recommended as increased switching noise is present.

9.4.2 LVPECL Outputs

When using an LVPECL output it is not recommended to place a capacitor to ground on the output as might be done when using a capacitor input LC lowpass filter. The capacitor will appear as a short to the LVPECL output drivers which are able to supply large amounts of switching current. The effect of the LVPECL sourcing large switching currents can result in the following:

1. Large switching currents through the Vcc pin of the LVPECL power supply resulting in more Vcc noise and possible Vcc spikes.
2. Large switching currents injected into the ground plane through the capacitor which could couple onto other Vcc pins with bypass capacitors to ground resulting in more Vcc noise and possible Vcc spikes.

9.4.3 Sharing MICROWIRE (SPI) Lines

When CLKuWire and DATAuWire toggle and an internal VCO mode is used, there may some spurious content on the phase noise plot related to the frequency of the CLKuWire and DATAuWire pins.