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ZHCSFH5A March 2016 – September 2016 ISO7821LLS

PRODUCTION DATA.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CCx	Supply voltage⁽²⁾	V_CC1, V_CC2	–0.5	6	V
V	Voltage on input, output, and enable pins	OUTx, INx, ENx	–0.5	V_CCx + 0.5⁽³⁾	V
I_O	Maximum current through OUTx pins		–20	20	mA
T_J	Junction temperature		–55	150	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground pin (GND1 or GND2) and are peak voltage values.

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC1, V_CC2	Supply voltage		3	3.3	5.5	V
\|V_ID\|	Magnitude of RX input differential voltage	Driven with voltage sources on RX pins	100		600	mV
V_IC	RX input common-mode voltage	V_CC1, V_CC2 ≥ 3 V	0.5 \|V_ID\|		2.4 – 0.5 \|V_ID\|	V
R_L	TX far-end differential termination			100		Ω
DR	Signaling rate		50		150	Mbps
T_A	Ambient temperature		–55	25	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ISO7821LLS		UNIT
		DW (SOIC)	DWW (SOIC)
		16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	82	84.6	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	44.6	46.4	°C/W
R_θJB	Junction-to-board thermal resistance	46.6	55.3	°C/W
ψ_JT	Junction-to-top characterization parameter	17.8	18.7	°C/W
ψ_JB	Junction-to-board characterization parameter	46.1	54.5	°C/W
R_θJC(bottom)	Junction-to-case(bottom) thermal resistance	—	—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Ratings

V_CC1 = V_CC2 = 5.5 V, T_J = 150°C, C_L = 5 pF, R_L = 100-Ω differential, input a 75-MHz 50% duty-cycle square wave,
EN1 = EN2 = 5.5 V

PARAMETER		MAX	UNIT
P_D	Maximum power dissipation (both sides)	180	mW
P_D1	Maximum power dissipation (side 1)	90	mW
P_D2	Maximum power dissipation (side 2)	90	mW

6.6 Insulation Specifications

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	SPECIFICATION		UNIT
PARAMETER		TEST CONDITIONS	DW	DWW	UNIT
GENERAL
CLR	External clearance⁽¹⁾	Shortest terminal-to-terminal distance through air	>8	>14.5	mm
CPG	External creepage⁽¹⁾	Shortest terminal-to-terminal distance across the package surface	>8	>14.5	mm
DTI	Distance through the insulation	Minimum internal gap (internal clearance)	>21	>21	μm
CTI	Tracking resistance (comparative tracking index)	DIN EN 60112 (VDE 0303–11); IEC 60112; UL 746A	>600	>600	V
	Material group	According to IEC 60664-1	I	I
	Overvoltage category per IEC 60664-1	Rated mains voltage ≤ 600 V_RMS	I–IV	I–IV
	Overvoltage category per IEC 60664-1	Rated mains voltage ≤ 1000 V_RMS	I–III	I–IV
DIN V VDE V 0884–10 (VDE V 0884–10):2006–12⁽²⁾
V_IORM	Maximum repetitive peak isolation voltage	AC voltage (bipolar)	2121	2828	V_PK
V_IOWM	Maximum isolation working voltage	AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test; see Figure 1 and Figure 2	1500	2000	V_RMS
V_IOWM	Maximum isolation working voltage	DC voltage	2121	2828	V_DC
V_IOTM	Maximum transient isolation voltage	V_TEST = V_IOTM, t = 60 s (qualification) t = 1 s (100% production)	8000	8000	V_PK
V_IOSM	Maximum surge isolation voltage⁽³⁾	Test method per IEC 60065, 1.2/50 µs waveform, V_TEST = 1.6 × V_IOSM = 12800 V_PK (qualification)	8000	8000	V_PK
q_pd	Apparent charge⁽⁴⁾	Method a: After I/O safety test subgroup 2/3, V_ini = V_IOTM, t_ini = 60 s; V_pd(m) = 1.2 × V_IORM = 2545 V_PK (DW) and 3394 V_PK (DWW), t_m = 10 s	≤5	≤5	pC
		Method a: After environmental tests subgroup 1, V_ini = V_IOTM, t_ini = 60 s; V_pd(m) = 1.6 × V_IORM = 3394 V_PK (DW) and 4525 V_PK (DWW), t_m = 10 s	≤5	≤5
		Method b1: At routine test (100% production) and preconditioning (type test) V_ini = V_IORM, t_ini = 1 s; V_pd(m) = 1.875 × V_IORM= 3977 V_PK (DW) and 5303 V_PK (DWW), t_m = 1 s	≤5	≤5
C_IO	Barrier capacitance, input to output⁽⁵⁾	V_IO = 0.4 × sin (2πft), f = 1 MHz	~0.7	~0.7	pF
R_IO	Isolation resistance, input to output⁽⁵⁾	V_IO = 500 V, T_A = 25°C	>10¹²	>10¹²	Ω
		V_IO = 500 V, 100°C ≤ T_A ≤ 125°C	>10¹¹	>10¹¹
		V_IO = 500 V at T_S = 150°C	>10⁹	>10⁹
	Pollution degree		2	2
	Climatic category		55/125/21	55/125/21
UL 1577
V_ISO	Withstanding isolation voltage	V_TEST = V_ISO = 5700 V_RMS, t = 60 s (qualification); V_TEST = 1.2 × V_ISO = 6840 V_RMS, t = 1 s (100% production)	5700	5700	V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.

6.7 Safety-Related Certifications

VDE	CSA	UL	CQC	TUV
Plan to certify according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01	Plan to certify under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1	Plan to certify according to UL 1577 Component Recognition Program	Plan to certify according to GB 4943.1-2011	Plan to certify according to EN 61010-1:2010 (3rd Ed) and EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013
Reinforced insulation Maximum transient isolation voltage, 8000 V_PK; Maximum repetitive peak isolation voltage, 2121 V_PK (DW), 2828 V_PK (DWW); Maximum surge isolation voltage, 8000 V_PK	Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed., 800 V_RMS (DW package) and 1450 V_RMS (DWW package) max working voltage (pollution degree 2, material group I);	Single protection, 5700 V_RMS	Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 V_RMS maximum working voltage	5700 V_RMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 V_RMS (DW package) and 1000 V_RMS (DWW package)
	2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 V_RMS (354 V_PK) max working voltage (DW package)	Single protection, 5700 V_RMS		5700 V_RMS Reinforced insulation per EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013 up to working voltage of 800 V_RMS (DW package) and 1450 V_RMS (DWW package)
Certification planned	Certification planned	Certification planned	Certification planned	Certification planned

6.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER		TEST CONDITIONS	MAX	UNIT
DW PACKAGE
I_S	Safety input, output, or supply current	R_θJA = 82°C/W, V_I = 5.5 V, T_J = 150°C, T_A = 25°C, see Figure 3	277	mA
I_S	Safety input, output, or supply current	R_θJA = 82°C/W, V_I = 3.6 V, T_J = 150°C, T_A = 25°C, see Figure 3	423	mA
P_S	Safety input, output, or total power	R_θJA = 82°C/W, T_J = 150°C, T_A = 25°C, see Figure 5	1524	mW
T_S	Maximum safety temperature		150	°C
DWW PACKAGE
I_S	Safety input, output, or supply current	R_θJA = 84.6°C/W, V_I = 5.5 V, T_J = 150°C, T_A = 25°C, see Figure 4	269	mA
I_S	Safety input, output, or supply current	R_θJA = 84.6°C/W, V_I = 3.6 V, T_J = 150°C, T_A = 25°C, see Figure 4	410	mA
P_S	Safety input, output, or total power	R_θJA = 84.6°C/W, T_J = 150°C, T_A = 25°C, see Figure 6	1478	mW
T_S	Maximum safety temperature		150	°C

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a device installed on a High-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

6.9 DC Electrical Characteristics

(over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
GENERAL
I_IN(EN)	Leakage Current on ENx pins	Internal pullup on ENx pins		13	40	µA
V_CC+(UVLO)	Positive-going undervoltage-lockout (UVLO) threshold				2.25	V
V_CC–(UVLO)	Negative-going UVLO threshold		1.7			V
V_HYS(UVLO)	UVLO threshold hysteresis			0.2		V
V_EN(ON)	EN pin turn-on threshold				0.7 V_CCx	V
V_EN(OFF)	EN pin turn-off threshold		0.3 V_CCx			V
V_EN(HYS)	EN pin threshold hysteresis			0.1 V_CCx		V
CMTI	Common-mode transient immunity	V_I = V_CCI⁽¹⁾ or 0 V; V_CM = 1000 V, see Figure 22	100	120		kV/μs
LVDS TX
\|V_OD\|	TX DC output differential voltage	R_L = 100 Ω, see Figure 23	250	350	450	mV
∆V_OD	Change in TX DC output differential between logic 1 and 0 states	R_L = 100 Ω, see Figure 23	–10	0	10	mV
V_OC	TX DC output common-mode voltage	R_L = 100 Ω, see Figure 23	1.125	1.2	1.375	V
∆V_OC	TX DC common-mode voltage difference	R_L = 100 Ω, see Figure 23	–25	0	25	mV
I_OS	TX output short circuit current through OUTx	OUTx = 0			10	mA
I_OS	TX output short circuit current through OUTx	OUTxP = OUTxM			10	mA
I_OZ	TX output current when in high impedance	ENx = 0, OUTx from 0 to V_CCx	–5		5	µA
C_OUT	TX output pad capacitance on OUTx at 1 MHz	DW package: ENx = 0, DC offset = V_CC / 2, Swing = 200 mV, Frequency (f) = 1 MHz		10		pF
C_OUT	TX output pad capacitance on OUTx at 1 MHz	DWW package: ENx = 0, DC offset = V_CC / 2, Swing = 200 mV, Frequency (f) = 1 MHz		10		pF
LVDS RX
V_IC	RX input common mode voltage	V_CCx ≥ 3 V	0.5 \|V_ID\|	1.2	2.4 – 0.5 \|V_ID\|	V
V_IT1	Positive going RX input differential threshold	Across V_IC			50	mV
V_IT2	Negative going RX input differential threshold	Across V_IC	–50			mV
I_INx	Input current on INx	From 0 to V_CC (each input independently)		10	20	µA
I_INxP – I_INxM	Input current balance	From 0 to V_CC	–6		6	µA
C_IN	RX input pad capacitance on INx at 1 MHz	DW package: DC offset = 1.2 V, Swing = 200 mV, f = 1 MHz		6.6		pF
C_IN	RX input pad capacitance on INx at 1 MHz	DWW package: DC offset = 1.2 V, Swing = 200 mV, f = 1 MHz		7.5		pF

(1) V_CCI = Input-side V_CCx; V_CCO = Output-side V_CCx.

6.10 DC Supply Current Characteristics

(over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
I_CC1 I_CC2	Supply current side 1 and side 2	3 V < V_CC1, V_CC2 < 3.6 V	EN1 = EN2 = 0, OUTx floating, V_ID ≥ 50 mV	2.3	3.6	mA
			EN1 = EN2 = 0, OUTx floating, V_ID ≤ –50 mV	3.5	5.6
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≥ 50 mV	6.2	9.9
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≤ –50 mV	7.5	12
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 50 Mbps	7.6	12.1
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 125 Mbps	8.5	13.6
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 150 Mbps	8.9	14.2
		4.5 V < V_CC1, V_CC2 < 5.5 V	EN1 = EN2 = 0, OUTx floating, V_ID ≥ 50 mV	2.3	3.6
			EN1 = EN2 = 0, OUTx floating, V_ID ≤ –50 mV	3.6	5.7
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≥ 50 mV	6.6	10.5
			EN1 = EN2 = 1, R_L = 100-Ω differential, V_ID ≤ –50 mV	7.9	12.6
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 50 Mbps	8.3	13.2
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 125 Mbps	9.7	15.5
			EN1 = EN2 = 1, R_L = 100-Ω differential, data communication at 150 Mbps	10.3	16.4

6.11 Timing Requirements for Distortion Correction Scheme

Valid data = 8b10b like data with DC balance and bounded disparity. See Figure 25.

		MIN	MAX	UNIT
t_CALIB	Time to complete internal calibration, after exiting idle state. LVDS TX output is held high during this time. During this time valid data must be presented at the receiver.	250	750	µs
t_IDLE	The minimum duration of any idle state that must be maintained between valid data transmissions.	10		µs
t_{IDLE_OUT}	After a channel enters idle state, the internal calibration loses lock after this time, and the LVDS outputs are gated high.	200	600	ns

6.12 Switching Characteristics

(over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
LVDS CHANNEL
t_PLH t_PHL	Propagation delay time			17	25	ns
t_sk(o)	Channel-to-channel output skew time	Opposite directional channels, same voltage and temperature			4.5	ns
t_sk(pp)	Part-part skew	Same directional channels, same voltage and temperature			4.5	ns
t_CMset	Common-mode setting time after EN = 0 to EN = 1 transition	Common-mode capacitive load = 100 pF to 0.5 nF			20	µs
	Total eye closure	DC balanced data with maximum run length of 6 at 125 Mbps, RX V_ID = 350 mV_PP, 1 ns t_rf10%-90%, –40 < T_A < 125°C, 3 V < V_CC1, V_CC2 < 5 V			30%
	Total eye closure	DC balanced data with maximum run length of 6 at 150 Mbps, RX V_ID = 350 mV_PP, 1 ns t_rf 10%-90%, –40 < T_A < 125°C, 3 V < V_CC1, V_CC2 < 5 V			40%
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V, see Figure 21		0.2	9	µs
LVDS TX AND RX
t_rf	TX differential rise and fall times (20% to 80%)	See Figure 19	300	780	1380	ps
∆V_OC(pp)	TX common-mode voltage peak-to-peak at 100 Mbps			0	150	mV_PP
t_PLZ, t_PHZ	TX disable time—valid output to HiZ	See Figure 20		10	20	ns
t_PZH	TX enable time—HiZ to valid high output⁽²⁾	See Figure 20		10	20	ns
\|V_ID\|	Magnitude of RX input differential voltage for valid operation	Driven with voltage sources on RX pins, see figures in the Parameter Measurement Information section	100		600	mV
t_rf(RX)	Allowed RX input differential rise and fall times (20% to 80%)	See Figure 24		1	0.3 × UI⁽¹⁾	ns

(1) UI is the unit interval.

(2) The t_PZL parameter is not defined because of the distortion-correction scheme. See the Distortion-Correction Scheme section for more information.