10.1 Layout Guidelines

The high switching frequency and large switching currents of the LM27762 make the choice of layout important. Use the following steps as a reference to ensure the device is stable and maintains proper LED current regulation across its intended operating voltage and current range:

• Place C_IN on the top layer (same layer as the LM27762) and as close as possible to the device. Connecting the input capacitor through short, wide traces to both the VIN and GND pins reduces the inductive voltage spikes that occur during switching, which can corrupt the VIN line.
• Place C_CPOUT on the top layer (same layer as the LM27762) and as close as possible to the VOUT and GND pins. The returns for both C_IN and C_CPOUT must come together at one point, as close as possible to the GND pin. Connecting C_CPOUT through short, wide traces reduces the series inductance on the VCPOUT and GND pins that can corrupt the VCPOUT and GND lines and cause excessive noise in the device and surrounding circuitry.
• Place C₁ on top layer (same layer as the LM27762) and as close as possible to the device. Connect the flying capacitor through short, wide traces to both the C1+ and C1– pins.
• Place C_OUT+, C_OUT– on the top layer (same layer as the LM27762) and as close to the respective OUT pin as possible. For best performance the ground connection for C_OUT must connect back to the GND connection at the thermal pad of the device.
• Place R₁ to R₄ on the top layer (same layer as LM27762) and as close as possible to the respective FB pin. For best performance the ground connection of R₂, R₄ must connect back to the GND connection at the thermal pad of the device.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. These add parasitic inductance and resistance that results in inferior performance, especially during transient conditions.

10.2 Layout Example

Figure 16. LM27762 Layout Example
(Note: Pullup resistor for PGOOD not shown in example.)