米6体育平台手机版

ZHCSFK7A September 2016 – October 2016 TPS254900-Q1

PRODUCTION DATA.

6 Specifications

6.1 Absolute Maximum Ratings

Voltages are with respect to GND unless otherwise noted⁽¹⁾

			MIN	MAX	UNIT
	Voltage range	CS, CTL1, CTL2, EN, FAULT, ILIM_HI, ILIM_LO, IN, IMON, OVP_SEL, STATUS	–0.3	7	V
		DM_OUT, DP_OUT	–0.3	5.7
		BIAS, DM_IN, DP_IN, OUT	–0.3	18
	Continuous current	DM_IN to DM_OUT or DP_IN to DP_OUT	–100	100	mA
	Continuous current	OUT	Internally limited		mA
I_SRC	Continuous output source current	ILIM_HI, ILIM_LO, IMON	Internally limited		A
I_SNK	Continuous output sink current	FAULT, STATUS		25	mA
I_SNK	Continuous output sink current	CS	Internally limited		A
T_J	Operating junction temperature		–40	Internally limited	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2 000⁽²⁾	V
		Charged-device model (CDM), per AEC Q100-011	±750⁽³⁾
		IEC 61000-4-2 contact discharge, DP_IN and DM_IN⁽⁴⁾	±8 000
		IEC 61000-4-2 air discharge, DP_IN and DM_IN⁽⁴⁾	±15 000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) The passing level per AEC-Q100 Classification H2.

(3) The passing level per AEC-Q100 Classification C5

(4) Surges per IEC 61000-4-2, level 4, 1999 applied from DP_IN and DM_IN to output ground of the TPS254900Q1EVM-817 (SLUUBI0) evaluation module.

6.3 Recommended Operating Conditions

Voltages are with respect to GND unless otherwise noted.

			MIN	MAX	UNIT
V_(IN)	Supply voltage	IN	4.5	6.5	V
	Input voltage	CTL1, CTL2, EN, OVP_SEL	0	6.5	V
	Input voltage	DM_IN, DM_OUT, DP_IN, DP_OUT	0	3.6	V
I_(OUT)	Output continuous current	OUT (–40°C ≤ T_A ≤ 85°C)		3	A
I_(OUT)	Output continuous current	DM_IN to DM_OUT or DP_IN to DP_OUT	–30	30	mA
	Continuous output sink current	FAULT, STATUS		10	mA
R_{(ILIM_xx)}	Current-limit-set resistors		14.3	1000	kΩ
T_J	Operating junction temperature		–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS254900-Q1	UNIT
		RVC (WQFN)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	37.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	39.9	°C/W
R_θJB	Junction-to-board thermal resistance	11.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	11.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise noted, –40°C ≤ T_J ≤ 125°C and 4.5 V ≤ V_(IN) ≤ 6.5 V, V_(EN) = V_(CTL1)= V_(CTL2) = V_(IN), R_(FAULT) = R_(STATUS) = 10 kΩ, R_(IMON) = 2.55 kΩ, R_{(ILIM_HI)} = 19.1 kΩ, R_{(ILIM_LO)} = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OUT – POWER SWITCH
r_DS(on)	On-resistance⁽¹⁾	T_J = 25°C		45	55	mΩ
		–40°C ≤ T_J ≤ 85°C		45	69
		–40°C ≤T_J ≤ 125°C		45	77
I_lkg	Reverse leakage current	V_OUT = 6.5 V, V_IN = V_EN = 0 V, –40°C ≤ T_J ≤ 85°C, measure I_(IN)		0.01	2	µA
OUT – DISCHARGE
R_(DCHG)	Discharge resistance (mode change)		400	500	630	Ω
CTL1, CTL2, EN, OVP_SEL INPUTS
	Input pin rising logic threshold voltage		1	1.35	2	V
	Input pin falling logic threshold voltage		0.85	1.15	1.65	V
	Hysteresis⁽²⁾			200		mV
	Input current	Pin voltage = 0 V or 6.5 V	–1		1	µA
CURRENT LIMIT
I_OS	OUT short-circuit current limit	R_{(ILIM_LO)} = 210 kΩ	190	240	290	mA
		R_{(ILIM_LO)} = 80.6 kΩ	555	620	680
		R_{(ILIM_LO)} = 21.5 kΩ	2145	2300	2460
		R_{(ILIM_LO)} = 19.1 kΩ	2420	2590	2760
		R_{(ILIM_HI)} = 18.2 kΩ	2545	2720	2895
		R_{(ILIM_HI)} = 14.3 kΩ	3240	3455	3670
		R_{(ILIM_HI)} shorted to GND	5000	6500	8000
SUPPLY CURRENT
I_{(IN_OFF)}	Disabled IN supply current	V_(EN) = 0 V, V_(OUT) = 0 V, –40°C ≤ T_J ≤ 85°C, no 5.1-kΩ resistor (open) between BIAS and OUT		0.1	5	µA
I_{(IN_ON)}	Enabled IN supply current	SDP mode (CTL1, CTL2 = 0, 1)		170	250	µA
		CDP mode (CTL1, CTL2 = 1, 1)		200	280
		Client mode (CTL1, CTL2 = 0, 0)		120	210
UNDERVOLTAGE LOCKOUT, IN
V_(UVLO)	UVLO threshold voltage	IN rising	3.9	4.15	4.3	V
	Hysteresis⁽³⁾	T_J = 25°C		100		mV
FAULT
	Output low voltage	I_(FAULT) = 1 mA			100	mV
	Off-state leakage	V_(FAULT) = 6.5 V			2	µA
STATUS
	Output low voltage	I_(STATUS) = 1 mA			100	mV
	Off-state leakage	V_(STATUS) = 6.5 V			2	µA
THERMAL SHUTDOWN
T_(OTSD2)	Thermal shutdown threshold		155			°C
T_(OTSD1)	Thermal shutdown threshold in current-limit		135			°C
	Hysteresis⁽³⁾			20		°C
LOAD DETECT (V_CTL1 = V_CTL2 = V_IN)
I_(LD)	I_OUT load detection threshold	R_{(ILIM_LO)} = 80.6 kΩ, rising load current	585	650	715	mA
	Hysteresis⁽³⁾			50		mA
DM_IN AND DP_IN OVERVOLTAGE PROTECTION
V_{(OV_Data)}	Protection trip threshold	DP_IN and DM_IN rising	3.7	3.9	4.15	V
	Hysteresis⁽³⁾			100		mV
R_{(DCHG_Data)}	Discharge resistor after OVP(2)	DP_IN = DM_IN = 18 V, IN = 5 V or 0 V		200		kΩ
		DP_IN = DM_IN = 5 V, IN = 5 V		370
		DP_IN = DM_IN = 5 V, IN = 0		390
OUT OVERVOLTAGE PROTECTION
V_{(OV_OUT_LOW)}	Protection trip threshold	OUT rising	5.65	6	6.35	V
	Hysteresis⁽³⁾			90		mV
V_{(OV_OUT_HIGH)}	Protection trip threshold	OUT rising	6.6	6.95	7.3	V
	Hysteresis⁽³⁾			130		mV
R_{(DCHG_OUT)}	Discharge resistor	OUT = 18 V, IN = 5 V		55	85	kΩ
R_{(DCHG_OUT)}	Discharge resistor	OUT = 18 V, IN = 0		80	120	kΩ
CABLE COMPENSATION
I_(CS)	Sink current	Load = 3 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	234	246	258	µA
		Load = 2.4 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	187	197	207
		Load = 2.1 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	163	172	181
		Load = 1 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	77	82	87
CURRENT MONITOR OUTPUT (IMON)
I_(IMON)	Source current	Load = 3 A, 0 ≤ V_(IMON) ≤ 2.5 V	287	312	337	µA
		Load = 2.4 A, 0 ≤ V_(IMON) ≤ 2.5 V	230	250	270
		Load = 2.1 A, 0 ≤ V_(IMON) ≤ 2.5 V	201	218	235
		Load = 1 A, 0 ≤ V_(IMON) ≤ 2.5 V	94	104	114
		Load = 0.5 A, 0 ≤ V_(IMON) ≤ 2.5 V	44	52	60
HIGH-BANDWIDTH ANALOG SWITCH
R_{(HS_ON)}	DP and DM switch on-resistance	V_{(DP_OUT)} = V_{(DM_OUT)} = 0 V, I_{(DP_IN)} = I_{(DM_IN)} = 30 mA		3.2	6.5	Ω
R_{(HS_ON)}	DP and DM switch on-resistance	V_{(DP_OUT)} = V_{(DM_OUT)} = 2.4 V, I_{(DP_IN)} = I_{(DM_IN)} = –15 mA		3.8	7.6	Ω
\|ΔR_{(HS_ON)}\|	Switch resistance mismatch between DP and DM channels	V_{(DP_OUT)} = V_{(DM_OUT)} = 0 V, I_{(DP_IN)} = I_{(DM_IN)} = 30 mA		0.05	0.15	Ω
\|ΔR_{(HS_ON)}\|	Switch resistance mismatch between DP and DM channels	V_{(DP_OUT)} = V_{(DM_OUT)} = 2.4 V, I_{(DP_IN)} = I_{(DM_IN)} = –15 mA		0.05	0.15	Ω
C_{(IO_OFF)}	DP and DM switch off-state capacitance⁽⁴⁾	V_EN = 0 V, V_{(DP_IN)} = V_{(DM_IN)} = 0.3 V, Vac = 0.03 V_PP , f = 1 MHz		8.8		pF
C_{(IO_ON)}	DP and DM switch on-state capacitance⁽⁴⁾	V_{(DP_IN)} = V_{(DM_IN)} = 0.3 V, Vac = 0.03 V_PP, f = 1 MHz		10.9		pF
	Off-state isolation(3)	V_(EN) = 0 V, f = 250 MHz		8		dB
	On-state cross-channel isolation⁽⁴⁾	f = 250 MHz		30		dB
I_lkg(OFF)	Off-state leakage current	V_EN = 0 V, V_{(DP_IN)} = V _{(DM_IN)} = 3.6 V, V_{(DP_OUT)} = V_{(DM_OUT)} = 0 V, measure I_{(DP_OUT)} and I_{(DM_OUT)}		0.1	1.5	µA
BW	Bandwidth (–3 dB)⁽⁴⁾	R_(L) = 50 Ω		940		MHz
CHARGING DOWNSTREAM PORT DETECT
V_{(DM_SRC)}	DM_IN CDP output voltage	V_{(DP_IN)} = 0.6 V, –250 µA < I_{(DM_IN)} < 0 µA	0.5	0.6	0.7	V
V_{(DAT_REF)}	DP_IN rising lower window threshold for V_{(DM_SRC)} activation		0.36		0.4	V
	Hysteresis⁽⁴⁾			50		mV
V_{(LGC_SRC)}	DP_IN rising upper window threshold for VDM_SRC de-activation		0.8		0.88	V
V_{(LGC_SRC_HYS)}	Hysteresis⁽⁴⁾			100		mV
I_{(DP_SINK)}	DP_IN sink current	V_{(DP_IN)} = 0.6 V	40	75	100	µA

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately.

(2) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's product warranty.

(3) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's product warranty.

(4) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's product warranty.

6.6 Switching Characteristics

Unless otherwise noted –40°C ≤ T_J ≤ 125°C and 4.5 V ≤ V_(IN) ≤ 6.5 V, V_(EN) = V_(IN), V_(CTL1) = V_(CTL2) = V_(IN). R_(FAULT) = R_(STATUS) = 10 kΩ, R_(IMON) = 2.55 KΩ, R_{(ILIM_HI)} = 19.1 kΩ, R_{(ILIM_LO)} = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_r	OUT voltage rise time	V_(IN) = 5 V, C_(L) = 1 µF, R_(L) = 100 Ω	1.05	1.75	3.1	ms
t_f	OUT voltage fall time	V_(IN) = 5 V, C_(L) = 1 µF, R_(L) = 100 Ω	0.27	0.47	0.82	ms
t_on	OUT voltage turnon time	V_(IN) = 5 V, C_(L) = 1 µF, R_(L) = 100 Ω		7.5	11	ms
t_off	OUT voltage turnoff time	V_(IN) = 5 V, C_(L) = 1 µF, R_(L) = 100 Ω		2.7	5	ms
t_{(DCHG_S)}	Discharge hold time (mode change)	Time V_(OUT) < 0.7 V	1.1	2	2.9	s
t_(IOS)	OUT short-circuit response time⁽¹⁾	V_(IN) = 5 V, R_(SHORT) = 50 mΩ		2		µs
t_{(OC_OUT_FAULT)}	OUT FAULT deglitch time	Bidirectional deglitch applicable to current-limit condition only (no deglitch assertion for OTSD)	5.5	8.5	11.5	ms
t_pd	Analog switch propagation delay ⁽¹⁾	V_(IN) = 5 V		0.14		ns
t_(SK)	Analog switch skew between opposite transitions of the same port (t_PHL – t_PLH) ⁽¹⁾	V_(IN) = 5 V		0.02		ns
t_{(LD_SET)}	Load-detect set time	V_(IN) = 5 V	120	210	280	ms
t_{(LD_RESET)}	Load-detect reset time	V_(IN) = 5 V	1.8	3	4.2	s
t_{(OV_Data)}	DP_IN and DM_IN overvoltage protection response time			5		µs
t_{(OV_OUT)}	OUT overvoltage protection response time			0.3		µs
t_{(OV_D_FAULT)}	DP_IN and DM_IN FAULT-asserted degltich time		11	16	23	ms
	OUT FAULT-asserted degltich time		11	16	23	ms

(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

6.7 Typical Characteristics

T_A = 25°C, V_(IN)= 5 V, V_(EN) = 5 V, V_(CTL1) = V_(CTL2) = 5 V, FAULT and STATUS connect to V_(IN) via a 10-kΩ pullup resistor (unless stated otherwise)

V_(IN) = 5 V

Figure 1. Power Switch On-Resistance vs Temperature

V_(OUT) = 5 V

Measure I_(OUT)

Figure 2. Reverse Leakage Current vs Temperature

Figure 3. OUT Discharge Resistance (Mode Change) vs Temperature

V_(IN) = 5 V

Figure 5. OUT Short-Circuit Current Limit vs Temperature I

CTL1 = 1

CTL2 = 1

Figure 7. Disabled IN Supply Current vs Temperature

V_(IN) = 5 V

R_{(ILIM_LO)} = 80.6 kΩ

Figure 9. I_(OUT) Rising Load-Detect Threshold and OUT Short-Circuit Limit vs Temperature

V_(IN) = 5 V

Figure 11. OUT Overvoltage Protection Threshold vs Temperature

V_IN = 6.5 V

Figure 13. I_(CS) vs V_(CS) Voltage

V_IN = 4.5 V

Figure 15. I_(IMON) vs V_(CS) Voltage

Figure 4. OUT Discharge Resistance (OVP) vs Temperature

V_(IN) = 5 V

Figure 6. OUT Short-Circuit Current Limit vs Temperature II

CTL1 = 1

CTL2 = 1

Figure 8. Enabled IN Supply Current – CDP (11) vs Temperature

V_(IN) = 5 V

Figure 10. DP_IN Overvoltage Protection Threshold vs Temperature

V_(IN) = 5 V

V_(CS) = 25 V

Figure 12. I_(CS) vs Temperature

V_IN = 5 V

V_(IMON) = 25 V

Figure 14. I_(IMON) vs Temperature

Measured on EVM with 10-cm cable

Figure 16. Bypassing the TPS254900-Q1 Data Switch

R_(LOAD) = 5 Ω

C_(LOAD) = 10 µF

t = 2 ms/div

Figure 18. Turnon Response

Measured on EVM with 10-cm cable

Figure 17. Through the TPS254900-Q1 Data Switch

R_(LOAD) = 5 Ω

C_(LOAD) = 10 µF

t = 1 ms/div

Figure 19. Turnoff Response

R_{(ILIM_LO)} = 80.6 kΩ

t = 4 ms/div

Figure 20. Enable Into Short (SDP)

TPS254900-Q1 ShCircNoLoad(SDP)_SLUSCO9.gif

R_{(ILIM_LO)} = 80.6 kΩ

t = 2 ms/div

Figure 22. Short Circuit to No Load (SDP)

R_{(ILIM_HI)} = 19.1 kΩ

R(short) = 50 mΩ

t = 2 ms/div

Figure 24. Hot Short

R_{(ILIM_LO)} = 80.6 kΩ

t = 1 s/div

Figure 26. Load-Detection Reset Time

TPS254900-Q1 OUT-ShtToBatRecov_SLUSCO9.gif

t = 100 ms/div

Figure 28. OUT Short-to-Battery Recovery

TPS254900-Q1 DPIN-ShtToBatRecov_SLUSCO9.gif

R_(BIAS) = 5.1 kΩ

t = 100 ms/div

Figure 30. DP_IN Short-to-Battery Recovery

TPS254900-Q1 DPIN-ShtTo VbusRecov_SLUSCO9.gif

R_(BIAS) = 5.1 kΩ

t = 200 ms/div

Figure 32. DP_IN Short-to-V_BUS and Recovery

Figure 34. Off-State Data-Switch Isolation vs Frequency

TPS254900-Q1 En-Short(CDP)-TC_SLUSCO9.gif

R_{(ILIM_HI)} = 19.1 kΩ

t = 4 ms/div

Figure 21. Enable Into Short (CDP) – Thermal Cycling

TPS254900-Q1 ShCircNoLoad(CDP)_SLUSCO9.gif

R_{(ILIM_HI)} = 19.1 kΩ

t = 4 ms/div

Figure 23. Short Circuit to No Load (CDP)

R_{(ILIM_LO)} = 80.6 kΩ

t = 100 ms/div

Figure 25. Load-Detection Set Time

t = 4 ms/div

Figure 27. OUT Short to Battery

t = 4 ms/div

Figure 29. DP_IN Short to Battery

R_(BIAS) = 5.1 kΩ

t = 4 ms/div

Figure 31. DP_IN Short to V_BUS

Figure 33. Data Transmission Characteristics vs Frequency

Figure 35. On-State Cross-Channel Isolation vs Frequency