The LM5170-Q1 can synchronize to an external clock if F_{EX_CLK} is within ±20% of F_OSC. The SYNCIN clock pulse width should be in the range of 100 ns to 500 ns, with a high voltage level > 2 V and low voltage level < 1 V.

F_{EX_CLK} can be adjusted dynamically. However the LM5170-Q1 PLL takes approximately 500 µs to settle down to the newly asserted frequency. During the PLL transient, the instantaneous F_SW may temporarily drop by 25%. To avoid overstress during the transient, TI recommends the user to reduce the load current to less than 50% by lowering the ISETA voltage or ISETD duty, or to simply turn off the dual-channels by setting EN1 = EN2 = 0 when making an the external clock change.