Each channel of the LM5170-Q1 has a pulse width modulator (PWM) employing a high-speed comparator. It compares the RAMP pin signal and the COMP pin signal to produce the PWM duty cycle. Note that the COMP signal passes through a 1-V DC offset before it is applied to the PWM comparator, as shown in Figure 8-7. Owing to this DC offset, the duty cycle can reduce to zero when the COMP pin or SS pin is pulled lower than 1 V. The maximum duty cycle is limited by the 200-ns minimum off-time. Note that the programmed dead time may reduce the maximum duty cycle because it is additional to the minimum off-time. Therefore, the available maximum duty cycle, for both buck and boost mode operation, is determined by Equation 16.

Equation 16.

where

• t_DT is the dead time given by (15) or the adaptive dead time, whichever applicable.

This maximum duty cycle limits the minimum voltage step-down ratio in buck mode operation, and the maximum step-up ratio in boost mode operation.

Note that the maximum COMP voltage is clamped at approximately 1.5 V higher than the RAMP peak voltage. This prevents the COMP voltage from moving too far above the RAMP voltage which could cause longer recovery time during a large scale upward step load response.