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ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1

PRODUCTION DATA.

8.3.2 Initialization Setup

Use the following initialization sequence to setup the SN65DSI85-Q1. This sequence is required for proper operation of the device. Steps 9 through 11 in the sequence are optional.

For additional information see Figure 6.

Table 1. Initialization Sequence

INITIALIZATION SEQUENCE NUMBER	INITIALIZATION SEQUENCE DESCRIPTION
Init seq 1	Power on
Init seq 2	After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven to LP11 state
Init seq 3	Set EN pin to Low
Wait 10 ms ⁽¹⁾
Init seq 4	Tie EN pin to High
Wait 10 ms ⁽¹⁾
Init seq 5	Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI8x is not functional until the CSR registers are initialized)
Init seq 6	Set the PLL_EN bit (CSR 0x0D.0)
Wait 10 ms ⁽¹⁾
Init seq 7	Set the SOFT_RESET bit (CSR 0x09.0)
Wait 10 ms ⁽¹⁾
Init seq 8	Change DSI data lanes to HS state and start DSI video stream
Wait 5 ms ⁽¹⁾
Init seq 9	Read back all resisters and confirm they were correctly written
Init seq 10	Write 0xFF to CSR 0xE5 to clear the error registers
Wait 1 ms ⁽¹⁾
Init seq 11	Read CSR 0xE5. If CSR 0xE5!= 0x00, then go back to step #2 and re-initialize

(1) Minimum recommended delay. This value can be exceeded.