ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0x18 is shown in Figure 27 and described in Table 16.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DE_NEG_POLARITY | HS_NEG_POLARITY | VS_NEG_POLARITY | LVDS_LINK_CFG | CHA_24BPP_MODE | CHB_24BPP_MODE | CHA_24BPP_FORMAT1 | CHB_24BPP_FORMAT1 |
| R/W-0 | R/W-1 | R/W-1 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
| BIT | FIELD | TYPE | RESET | DESCRIPTION | |
|---|---|---|---|---|---|
| 7 | DE_NEG_POLARITY | R/W | 0 |
0: DE is positive polarity driven 1 during active pixel transmission on LVDS (default) 1: DE is negative polarity driven 0 during active pixel transmission on LVDS |
|
| 6 | HS_NEG_POLARITY | R/W | 1 |
0: HS is positive polarity driven 1 during corresponding sync conditions 1: HS is negative polarity driven 0 during corresponding sync (default) |
|
| 5 | VS_NEG_POLARITY | R/W | 1 |
0: VS is positive polarity driven 1 during corresponding sync conditions 1: VS is negative polarity driven 0 during corresponding sync (default) |
|
| 4 | LVDS_LINK_CFG | R/W | 1 |
0: LVDS Channel A and Channel B outputs enabled
1: LVDS Single-Link configuration; Channel A output enabled and Channel B output disabled (default) |
|
| 3 | CHA_24BPP_MODE | R/W | 0 |
0: Force 18 bpp; LVDS channel A lane 4 (A_Y3P or A_Y3N) is disabled (default) 1: Force 24 bpp; LVDS channel A lane 4 (B_Y3P or B_Y3N) is enabled |
|
| 2 | CHB_24BPP_MODE | R/W | 0 |
0: Force 18bpp; LVDS channel B lane 4 (A_Y3P or A_Y3N) is disabled (default) 1: Force 24bpp; LVDS channel B lane 4 (B_Y3P or B_Y3N) is enabled |
|
| 1 | CHA_24BPP_FORMAT1 | R/W | 0 | This field selects the 24-bpp data format
Note 1: This field must be 0 when 18-bpp data is received from DSI. Note 2: If this field is set to 1 and CHA_24BPP_MODE is 0, the SN65DSI85-Q1 device converts 24-bpp data to 18-bpp data for transmission to an 18-bpp panel. In this configuration, the SN65DSI85-Q1 device does not transmit the two LSB per color on LVDS channel A, because LVDS channel A lane A_Y3P or A_Y3N is disabled. 0: LVDS channel A lane A_Y3P or A_Y3N transmits the two most significant bits (MSB) per color; Format 2 (default) 1: LVDS channel A lane A_Y3P or A_Y3N transmits the two least significant bits (LSB) per color; Format 1 |
|
| 0 | CHB_24BPP_FORMAT1 | R/W | 0 | This field selects the 24-bpp data format
Note 1: This field must be 0 when 18-bpp data is received from DSI. Note 2: If this field is set to 1 and CHB_24BPP_MODE is 0, the SN65DSI85-Q1 device converts 24-bpp data to 18-bpp data for transmission to an 18-bpp panel. In this configuration, the SN65DSI85-Q1 device does not transmit the two LSB per color on LVDS channel B, because LVDS channel B lane B_Y3P or B_Y3N is disabled. 0: LVDS channel B lane B_Y3P or B_Y3N transmits the two most significant bits (MSB) per color; Format 2 (default) 1: LVDS channel B lane B_Y3P or B_Y3N transmits the two least significant bits (LSB) per color; Format 1 |
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