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ZHCSFT4A March 2016 – August 2016 ISO7820LL , ISO7821LL

PRODUCTION DATA.

8 Detailed Description

8.1 Overview

The ISO782xLL is a family of isolated LVDS buffers. The differential signal received on the LVDS input pins is first converted to CMOS logic levels. The signal is then transmitted across a silicon-dioxide (SiO₂) based capacitive-isolation barrier using an on-off keying (OOK) modulation scheme. A high frequency carrier transmitted across the barrier represents one logic state and an absence of a carrier represents the other logic state. On the other side of the barrier a demodulator converts the OOK signal back to logic levels, which is then converted to LVDS outputs by a differential driver. These devices incorporate advanced circuit techniques to maximize CMTI performance and minimize radiated emissions.

The ISO782xLL family of devices is TIA/EIA-644-A standard compliant. The LVDS transmitters drive a minimum differential-output voltage magnitude of 250 mV into a 100-Ω load, and the LVDS receivers are capable of detecting differential signals ≥50 mV in magnitude. The device consumes 10 mA per channel at 100 Mbps with 5-V supplies.

The Functional Block Diagram section shows a conceptual block diagram of one channel of the ISO782xLL family of devices.

8.2 Functional Block Diagram

8.3 Feature Description

The ISO782xLL family of devices is available in two channel configurations with a default differential high-output state.

PART NUMBER	CHANNEL DIRECTION	RATED ISOLATION	MAXIMUM DATA RATE	DEFAULT DIFFERENTIAL OUTPUT
ISO7820LL	2 Forward	5700 V_RMS / 8000 V_PK ⁽¹⁾	100 Mbps	High
ISO7821LL	1 Forward, 1 Reverse	5700 V_RMS / 8000 V_PK ⁽¹⁾	100 Mbps	High

(1) See the Safety-Related Certifications section for detailed isolation ratings.

8.4 Device Functional Modes

Table 1 lists the functional modes for the ISO782xLL family of devices.

Table 1. ISO782xLL Function Table⁽¹⁾

V_CCI	V_CCO	INPUT (INx±)⁽²⁾	OUTPUT ENABLE (ENx)	OUTPUT (OUTx±)⁽³⁾	COMMENTS
PU	PU	H	H or open	H	Normal Operation: A channel output assumes the logic state of the input.
		L	H or open	L
		I	H or open	H or L
X	PU	X	L	Z	A low-logic state at the output enable causes the outputs to be in high impedance.
PD	PU	X	H or open	H	Default mode: When V_CCI is unpowered, a channel output assumes the logic high state. When V_CCI transitions from unpowered to powered up, a channel output assumes the logic state of the input. When V_CCI transitions from powered up to unpowered, a channel output assumes the selected default high state.
X	PD	X	X	Undetermined	When V_CCO is unpowered, a channel output is undetermined. When V_CCO transitions from unpowered to powered-up, a channel output assumes the logic state of the input

(1) V_CCI = input-side V_CC; V_CCO = output-side V_CC; PU = powered up (V_CCx ≥ 2.25 V); PD = powered down (V_CCx ≤ 1.7 V); X = irrelevant

(2) Input (INx±): H = high level (V_ID ≥ 50 mV); L = low level (V_ID ≤ –50 mV); I = indeterminate (–50 mV < V_ID < 50 mV)

(3) Output (OUTx±): H = high level (V_OD ≥ 250 mV); L = low level (V_OD ≤ –250 mV); Z = high impedance.

8.4.1 Device I/O Schematics

ISO7820LL ISO7821LL device_IO_sllset8.gif

Figure 28. Device I/O Schematics