The SER has a PDB input pin to ENABLE or power down the device. Enabling PDB on the SER disables the link to save power. If PDB = HIGH, the SER operates at its internal default oscillator frequency when the input PCLK stops. When the PCLK starts again, the SER locks to the valid input PCLK and transmit the data to the DES. When PDB = LOW, the high-speed driver outputs are static HIGH. See Section 8.1.2 for power-up requirements.