米6体育平台手机版

ZHCSFV6E august 2016 – november 2020 DS90UB933-Q1

PRODUCTION DATA

6.6 Recommended Serializer Timing For PCLK

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾ ⁽²⁾

PARAMETER		TEST CONDITIONS	PIN / FREQ	MIN	NOM	MAX	UNIT
t_TCP	Transmit clock period	10-bit mode 50 MHz – 100 MHz		7.52	T	20	ns
t_TCP	Transmit clock period	12-bit mode 37.5 MHz - 100 MHz		10	T	26.67	ns
t_TCIH	Transmit clock input high time			0.4T	0.5T	0.6T
t_TCIL	Transmit clock input low time			0.4T	0.5T	0.6T
t_CLKT	PCLK input transition time (Figure 6-7)	10-bit mode 50 MHz – 100 MHz		0.05T	0.25T	0.3T
t_CLKT	PCLK input transition time (Figure 6-7)	12-bit mode 37.5 MHz – 100 MHz		0.05T	0.25T	0.3T
t_JIT0	PCLK input jitter ⁽³⁾ (PCLK from imager mode)	LPF = ƒ/20, CDR PLL Loop BW = ƒ/15, BER = 1E-10	ƒ_PCLK = 37.5 – 100 MHz⁽⁵⁾			0.45	UI
t_JIT1	PCLK input jitter⁽³⁾ (External oscillator mode)	LPF = ƒ/20, CDR PLL Loop BW = ƒ/15, BER = 1E-10	ƒ_PCLK = 37.5 – 100 MHz⁽⁵⁾		1T
t_JIT2	External oscillator jitter⁽³⁾⁽⁴⁾	LPF = ƒ/20, CDR PLL Loop BW = ƒ/15, BER = 1E-10, paired with DS90UB934-Q1 deserializer	ƒ_OSC = 25 – 66.67 MHz⁽⁶⁾			0.45	UI
Δ_OSC	External Oscillator Frequency Stability		ƒ_OSC = 25 – 66.67 MHz⁽⁶⁾		±50		ppm
t_DC	CLKOUT duty cycle (external oscillator mode)		ƒ_OSC = 25 – 66.67 MHz⁽⁶⁾	45%	50%	55%

(1) Recommended input timing requirements are input specifications and not tested in production.

(2) T is the period of the PCLK.

(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, T_A = 25°C, and at Section 6.3 at the time of product characterization and are not verified.

(4) 0.45UI maximum when used with DS90UB934-Q1 deserializer. When used with DS90UB914A-Q1 deserializer, the maximum is 0.3UI.

(5) ƒ_PCLK denotes input PCLK frequency to the device.

(6) ƒ_OSC denotes input external oscillator frequency to the device (GPO3/CLKIN).