ZHCSFV6E august   2016  – november 2020 DS90UB933-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Serializer Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB933/934
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS V(VDDIO) Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB933/934 Operation With External Oscillator as Reference Clock
      2. 7.4.2 DS90UB933/934 Operation With Pixel Clock From Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built-In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 IDX Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 62
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Interconnect Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表

Pin Functions

PINI/ODESCRIPTION
NAMENO.
LVCMOS PARALLEL INTERFACE
DIN[0:11]19,20,21,22,
23,24,26,27,
29,30,31,32		Inputs, LVCMOS
w/ pulldown		Parallel data Inputs. For 10-bit MODE, parallel inputs DIN[0:9] are active. DIN[10:11] are inactive and should not be used. Any unused inputs (including DIN[10:11]) must be No Connect. For 12-bit MODE, parallel inputs DIN[0:11] are active. Any unused inputs must be No Connect.
HSYNC1Input, LVCMOS
w/ pulldown		Horizontal SYNC input. Note: HS transition restrictions: 1. 12-bit mode: No HS restrictions (raw) 2. 10-bit mode: HS restricted to no more than one transition per 10 PCLK cycles. Leave open if unused.
VSYNC2Input, LVCMOS
w/ pulldown		Vertical SYNC input. Note: VS transition restrictions: 1. 12-bit mode: No VS restrictions (raw) 2. 10-bit mode: VS restricted to no more than one transition per 10 PCLK cycles. Leave open if unused.
PCLK3Input, LVCMOS
w/ pulldown		Pixel clock input pin. Strobe edge set by TRFB control register 0x03[0].
GENERAL PURPOSE OUTPUT (GPO)
GPO[1:0]16,15Output, LVCMOSGeneral-purpose output pins can be configured as outputs, used to control and respond to various commands. GPO[1:0] can be configured to be the outputs for input signals coming from GPIO[1:0] pins on the deserializer or can be configured to be outputs of the local register on the serializer. Leave open if unused.
GPO[2]/
CLKOUT		17Output, LVCMOSGPO[2] pin can be configured to be the output for input signal coming from the GPIO[2] pin on the deserializer or can be configured to be the output of the local register on the Serializer. It can also be configured to be the output clock pin when the DS90UB933-Q1 device is used in the external oscillator mode. See Section 7.4 for a detailed description of External Oscillator mode. It is recommended to pull GPO2 to GND with a minimum 40-kΩ resistor to ensure GPO2=LOW when PDB transitions from LOW to HIGH.
GPO[3]/
CLKIN		18Input/Output, LVCMOSGPO[3] can be configured to be the output for input signals coming from the GPIO[3] pin on the deserializer or can be configured to be the output of the local register setting on the serializer. It can also be configured to be the input clock pin when the DS90UB933-Q1 serializer is working with an external oscillator. See Section 7.4 for a detailed description of external oscillator mode. Leave open if unused.
BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE
SCL4Input/Output,
Open Drain		Clock line for the bidirectional control bus communication
SCL requires an external pullup resistor to V(VDDIO).
SDA5Input/Output,
Open Drain		Data line for the bidirectional control bus communication
SDA requires an external pullup resistor to V(VDDIO).
MODE8Input, analogDevice mode select
Resistor (Rmode) to ground and 10-kΩ pullup to 1.8 V rail. MODE pin on the serializer can be used to select whether the system is running off the PCLK from the imager or an external oscillator. See details in Table 7-2.
IDX6Input, analogDevice ID Address Select
The IDX pin on the serializer is used to assign the I2C device address. Resistor (RID) to Ground and 10-kΩ pullup to 1.8 V rail. See Table 7-6.
CONTROL AND CONFIGURATION
PDB9Input, LVCMOS
w/ pulldown		Power-down mode input pin
PDB = H, Serializer is enabled and is ON.
PDB = L, Serializer is in power down mode. When the serializer is in power down, the PLL is shut down, and IDD is minimized. Programmed control register data is NOT retained and reset to default values.
RES7Input, LVCMOS
w/ pulldown		Reserved
This pin MUST be tied LOW.
FPD–Link III INTERFACE
DOUT+13Input/Output, CMLNon-inverting differential output, bidirectional control channel input. The interconnect must be AC coupled with a 0.1-µF capacitor.
DOUT-12Input/Output, CMLInverting differential output, bidirectional control channel input. The interconnect must be AC coupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect, place a 0.047-µF AC-coupling capacitor in series with a 50-Ω resistor before terminating to GND.
POWER AND GROUND(1)
VDDPLL10Power, AnalogPLL power, 1.8 V ±5%.
VDDT11Power, AnalogTx analog power, 1.8 V ±5%.
VDDCML14Power, AnalogCML and bidirectional channel driver power, 1.8 V ±5%.
VDDD28Power, DigitalDigital Power, 1.8 V ±5%.
VDDIO25Power, DigitalPower for I/O stage. The single-ended inputs and SDA, SCL are powered from V(VDDIO). VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%.
VSSDAPGround, DAPDAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.
(1) See Section 8.1.2.
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