ZHCSFY1F December   2016  – April 2024 TDP158

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Power Supply
    6. 5.6  Electrical Characteristics, Differential Input
    7. 5.7  Electrical Characteristics, TMDS Differential Output
    8. 5.8  Electrical Characteristics, DDC, I2C, HPD, and ARC
    9. 5.9  Electrical Characteristics, TMDS Differential Output in DP-Mode
    10. 5.10 Switching Characteristics, TMDS
    11. 5.11 Switching Characteristics, HPD
    12. 5.12 Switching Characteristics, DDC and I2C
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reset Implementation
      2. 7.3.2  Operation Timing
      3. 7.3.3  Lane Control
      4. 7.3.4  Swap
      5. 7.3.5  Main Link Inputs
      6. 7.3.6  Receiver Equalizer
      7. 7.3.7  Input Signal Detect Block
      8. 7.3.8  Transmitter Impedance Control
      9. 7.3.9  TMDS Outputs
      10. 7.3.10 Slew Rate Control
      11. 7.3.11 Pre-Emphasis
      12. 7.3.12 DP-Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Training for HDMI 2.0 Data Rate Monitor
      2. 7.4.2 DDC Functional Description
    5. 7.5 Register Maps
      1. 7.5.1  Local I2C Control BIT Access TAG Convention
      2. 7.5.2  BIT Access Tag Conventions
      3. 7.5.3  CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
      4. 7.5.4  CSR Bit Field Definitions, REV_ID (address = 08h )
      5. 7.5.5  CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
      6. 7.5.6  CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
      7. 7.5.7  CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
      8. 7.5.8  CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
      9. 7.5.9  CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
      10. 7.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
      11. 7.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
      12. 7.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
      13. 7.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
      14. 7.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
      15. 7.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
      16. 7.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
      17. 7.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
      18. 7.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
      19. 7.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source Side
        2. 8.2.2.2 DDC Pull Up Resistors
      3. 8.2.3 Application Curves
      4. 8.2.4 Application with DDC Snoop
        1. 8.2.4.1 Source Side HDMI Application
      5. 8.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Management
      2. 8.3.2 Standby Power
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

GUID-EFB5333D-1B2E-4E36-A543-97F14D0F539B-low.svg Figure 4-1 RSB Package, 40-Pin WQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
SUPPLY AND GROUND PINS
VCC 11, 37 P 3.3V Power Supply
VDD 12,20,31,40 P 1.1V Power Supply
GND 15, 35 Thermal Pad G Ground
MAIN LINK INPUT PINS
IN_D2p/n 1, 2 I Channel 2 Differential Input
IN_D1p/n 4, 5 I Channel 1 Differential Input
IN_D0p/n 6, 7 I Channel 0 Differential Input
IN_CLKp/n 9, 10 I Clock Differential Input
MAIN LINK OUTPUT PINS (FAIL SAFE)
OUT_D2n/p 29, 30 O TMDS Data 2 Differential Output
OUT_D1n/p 26, 27 O TMDS Data 1 Differential Output
OUT_D0n/p 24, 25 O TMDS Data 0 Differential Output
OUT_CLKn/p 21, 22 O TMDS Data Clock Differential Output
HOT PLUG DETECT AND DDC PINS
HPD_SRC 3 O Hot Plug Detect Output to source side
HPD_SNK 28 I Hot Plug Detect Input from sink side
SDA_SNK 33 I/O Sink Side Bidirectional DDC Data Line
SCL_SNK 32 I/O Sink Side Bidirectional DDC Clock Line
SDA_SRC 39 I/O Source Side Bidirectional DDC Data Line
SCL_SRC 38 I/O Source Side Bidirectional DDC Clock Line
CONTROL PINS
OE 36 I Operation Enable/Reset Pin
OE = L: Power Down Mode
OE = H: Normal Operation
Internal weak pullup: Resets device when transitions from H to L
I2C_EN 8 I I2C_EN = High; Puts Device into I2C Control Mode
I2C_EN = Low; Puts Device into Pin Strap Mode
SDA_CTL/PRE 14 I/0 I2C Data Signal: When I2C_EN = High;
Pre-emphasis: When I2C_EN = Low: See Section 7.3.11
DE = L: None 0dB
DE = H: 3.5dB
SCL_CTL/SWAP 13 I I2C Clock Signal: When I2C_EN = High;
Lane SWAP: When I2C_EN = Low: See Section 7.3.4 HDMI Mode Only
SWAP = L: Normal Operation
SWAP = H: Lane Swap
VSADJ 18 I TMDS Compliant Voltage Swing Control (Nominal 6 kΩ for HDMI and DP combination; 6.49 kΩ for HDMI only)
A0/EQ1 17 I
3 Level		 Address Bit 1 for I2C Programming when I2C_EN = High
EQ1 Pin Setting when I2C_EN = Low; Works in conjunction with A1/EQ2; See Section 7.3.5 for settings. For pin control, Low = 1kΩ pulldown resistor to GND, High = 1kΩ pullup resistor to VCC, NC = Floating.
A1/EQ2 23 I
3 Level		 Address Bit 2 for I2C Programming when I2C_EN = High
EQ2 Pin Setting when I2C_EN = Low; Works in conjunction with A0/EQ1; See Section 7.3.5 for settings. For pin control, Low = 1kΩ pulldown resistor to GND, High = 1kΩ pullup resistor to VCC, NC = Floating.
SLEW 34 I
3 Level		 Clock Slew Rate Control: See Section 7.3.10
SLEW = L: Slowest ≅ 203ps
SLEW = NC (Default): Mid-range 1 ≅ 180ps
SLEW = H: Fastest ≅ 122ps
For pin control, L = 1kΩ pulldown resistor to GND, H = 1kΩ pullup resistor to VCC, NC = Floating.
TERM 16 I
3 Level		 Source Termination Control: See Section 7.3.8
TERM = H, 75Ω ≅ 150Ω
TERM = L, Transmit Termination impedance in 150Ω ≅ 300Ω
TERM = NC, No transmit Termination
Note: When TMDS_CLOCK_RATIO_STATUS bit = 1 the TDP158 sets source termination to 75Ω ≅ 150Ω Automatically
For pin control, L = 1kΩ pulldown resistor to GND, H = 1kΩ pullup resistor to VCC, NC = Floating.
NC 19 NA No Connect. Optionally connect 0.1μF to GND to reduce noise.
(1) I= Input, O = Output, P = Power, G = Ground
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